// Verilog model created from schematic cv_test.sch
// 2002/06/04 7:14:56 PM
// vericode v2.1


     // Schematic 'cv_test.sch'
module cv_test;
  wire [1:0]  X_O;
  wire [1:0]  Y_O;
  wire [12:0]  DATA;
  wire [11:0]  XM;
  wire [3:0]  CV_VALUE;
  wire  CLK;
  wire  RESET;
  wire  LEFT;
  wire  NSPAN;
  wire  CYC;
  wire  MASK15;

cv CV (.CV_VALUE(CV_VALUE[3:0]), .CYCLE_TYPE(CYC), .EW_CV_DATA(DATA[12:0]),
           .EW_CV_NEWSPAN(NSPAN), .EW_CV_START_X(XM[11:0]), .GCLK(CLK),
           .LEFT(LEFT), .MASK15(MASK15), .RESET_L(RESET), .X_DITHER(X_O[1:0]),
           .X_OFFSET(Y_O[1:0]));
driver DRIVER (.CYCLE_TYPE(CYC), .EW_CV_DATA(DATA[12:0]), .EW_CV_NEWSPAN(NSPAN),
           .GCLK(CLK), .LEFT(LEFT), .RESET(RESET), .X_MAJOR(XM[11:0]));

endmodule