Makefile
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#!smake -J 5
PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs
#
# Directories
#
HW = hw2
TCTM = ../..
INDATA = ../../InData
RTLOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/tc/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/tm/src \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
+libext+.v+.vzd \
+incdir+$(PRDEPTH)/$(HW)/chip/rcp/inc
SYNOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/tc/syn \
-y $(PRDEPTH)/$(HW)/chip/rcp/tm/syn \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
+libext+.v+.vzd+.vsyn
LDIRT = driver*.v *.mem *.out vcs.log *.dump $(TMPDIR)/$(USER)_tc_frac018 $(TMPDIR)/$(USER)_tc_frac018_syn *.tab simv*
RTESTS = tc_frac018
STESTS = tc_frac018_syn
FAST = fast018
ERROR = \
@if grep "ERROR IN SIMULATION" FILE ; \
then \
echo ""; \
else \
echo "NO ERRORS IN SIMULATION"; \
fi
default: $(RTESTS)
stests: $(STESTS)
include $(PRDEPTH)/PRrules
.mem.out :
$(RTESTS): simv018
$(STESTS): simv018_syn
tc_frac018.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp008.tab $@.base.Z
(cd ../..; make test018)
/usr/bsd/uncompress $@.base.Z
cmp $@ $@.base
/usr/bsd/compress $@.base
driver018.v: tc_frac018.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 tc_frac018.tab > driver018.v
simv018: top_level.v driver018.v tc_frac018.mem $(_FORCE)
$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv018 -Mdir="$(TMPDIR)/$(USER)_tc_frac018" top_level.v driver018.v
@ if [ "$(DUMP)" ]; \
then \
(echo "simv018 +mem=tc_frac018.mem > simv018.out"; simv018 -vcd verilog018.dump +mem=tc_frac018.mem > simv018.out;) \
else \
(echo "simv018 +mem=tc_frac018.mem > simv018.out"; simv018 +mem=tc_frac018.mem +vcs+dumpvarsoff > simv018.out;) \
fi
$(ERROR:FILE=simv018.out)
$(LOG_ERROR)
simv018_syn: top_level.vsyn driver018.v tc_frac018.mem $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
$(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
-Mdir="$(TMPDIR)/$(USER)_tc_frac018_syn" \
top_level.vsyn driver018.v
@ if [ "$(DUMP)" ]; \
then \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tc_frac018.mem > $@.out"; $@ -vcd verilog018_syn.dump +mem=tc_frac018.mem > $@.out;) \
else \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tc_frac018.mem > $@.out"; $@ +mem=tc_frac018.mem +vcs+dumpvarsoff > $@.out;) \
fi
$(ERROR:FILE=simv018_syn.out)
$(LOG_ERROR)
fast: $(FAST)
fast018: tc_frac018.mem
simv018 +mem=$? | tee $*.out