Makefile
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#!smake -J 5
PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs
#
# Directories
#
HW = hw2
TCTM = ../..
INDATA = ../../InData
RTLOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/tc/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/tm/src \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
+libext+.v+.vzd \
+incdir+$(PRDEPTH)/$(HW)/chip/rcp/inc
SYNOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/tc/syn \
-y $(PRDEPTH)/$(HW)/chip/rcp/tm/syn \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
+libext+.v+.vzd+.vsyn
LDIRT = driver*.v *.mem *.out vcs.log *.dump $(TMPDIR)/$(USER)_tc_tilemem015 $(TMPDIR)/$(USER)_tc_tilemem015_syn *.tab simv*
RTESTS = tc_tilemem015
STESTS = tc_tilemem015_syn
FAST = fast015
ERROR = \
@if grep "ERROR IN SIMULATION" FILE ; \
then \
echo ""; \
else \
echo "NO ERRORS IN SIMULATION"; \
fi
default: $(RTESTS)
stests: $(STESTS)
include $(PRDEPTH)/PRrules
.mem.out:
$(RTESTS): simv015
$(STESTS): simv015_syn
tc_tilemem015.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp005.tab $@.base.Z
(cd ../..; make test015)
/usr/bsd/uncompress $@.base.Z
cmp $@ $@.base
/usr/bsd/compress $@.base
driver015.v: tc_tilemem015.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 tc_tilemem015.tab > driver015.v
simv015: top_level.v driver015.v tc_tilemem015.mem $(_FORCE)
$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv015 -Mdir="$(TMPDIR)/$(USER)_tc_tilemem015" top_level.v driver015.v
@ if [ "$(DUMP)" ]; \
then \
(echo "simv015 +mem=tc_tilemem015.mem > simv015.out"; simv015 -vcd verilog015.dump +mem=tc_tilemem015.mem > simv015.out;) \
else \
(echo "simv015 +mem=tc_tilemem015.mem > simv015.out"; simv015 +mem=tc_tilemem015.mem +vcs+dumpvarsoff > simv015.out;) \
fi
$(ERROR:FILE=simv015.out)
$(LOG_ERROR)
simv015_syn: top_level.vsyn driver015.v tc_tilemem015.mem $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
-Mdir="$(TMPDIR)/$(USER)_tc_tilemem015_syn" top_level.vsyn driver015.v
@ if [ "$(DUMP)" ]; \
then \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tc_tilemem015.mem > $@.out"; $@ -vcd verilog015_syn.dump +mem=tc_tilemem015.mem > $@.out;) \
else \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tc_tilemem015.mem > $@.out"; $@ +mem=tc_tilemem015.mem +vcs+dumpvarsoff > $@.out;) \
fi
$(ERROR:FILE=simv015_syn.out)
$(LOG_ERROR)
fast: $(FAST)
fast015: tc_tilemem015.mem
simv015 +mem=$? | tee $*.out