#!/bin/csh -f
#
#  Shell script for generating tabular trace file 
#
#  Usage: do_sim <test>
#
#
#  11/9/94   TD
#

if ( $#argv != 1 ) then
  echo "Usage: $0 <test>"
  exit
endif

vlsishell << EOF
set echo on

####################################
# invoke qsim and load netlist
####################################
qsim
mode compassqsim
load [nls]tex

####################################
# setup environment
####################################
radix 16
options bidirConflict
options failTestOnZ
#trace (static, tabular)
options tabularReportOnChange
trace (dynamic, tabular)

####################################
# display current environment
####################################
preprocess
simparms
options
trace
modeloptions

####################################
# bus and signal aliases
####################################

# common signals
vector l[15:0]
vector s[15:0]
vector t[15:0]
vector w[15:0]
vector min_level[4:0]
vector max_level[2:0]
vector prim_tile[2:0]
vector tile_adrs[2:0]
vector tile_data[47:0]
vector copy_load[63:0]
equiv  tm.copy_load_oe copy_load_oe

# tc_adj signals
#vector tc.adj_s.c_tile[16:0]
vector s_tile_diff_msb[9:5] tc.adj_s.tile_diff_reg[9].q tc.adj_s.tile_diff_reg[8].q tc.adj_s.tile_diff_reg[7].q tc.adj_s.tile_diff_reg[6].q tc.adj_s.tile_diff_reg[5].q
vector s_tile_diff_lsb[4:0] tc.adj_s.tile_diff_reg[4].q tc.adj_s.tile_diff_reg[3].q tc.adj_s.tile_diff_reg[2].q tc.adj_s.tile_diff_reg[1].q tc.adj_s.tile_diff_reg[0].q
vector tc.s_adrs[12:0]
vector tc.s_frac[4:0]
vector tc.s_all_zero[3:0]
vector tc.s_all_one[3:0]
#vector tc.adj_t.c_tile[16:0]
vector t_tile_diff_msb[9:5] tc.adj_t.tile_diff_reg[9].q tc.adj_t.tile_diff_reg[8].q tc.adj_t.tile_diff_reg[7].q tc.adj_t.tile_diff_reg[6].q tc.adj_t.tile_diff_reg[5].q
vector t_tile_diff_lsb[4:0] tc.adj_t.tile_diff_reg[4].q tc.adj_t.tile_diff_reg[3].q tc.adj_t.tile_diff_reg[2].q tc.adj_t.tile_diff_reg[1].q tc.adj_t.tile_diff_reg[0].q
vector tc.t_adrs[12:0]
vector tc.t_frac[4:0]
vector s_tile_msb[16:8]	tc.adj_s.c_tile_reg[16].q tc.adj_s.c_tile_reg[15].q tc.adj_s.c_tile_reg[14].q tc.adj_s.c_tile_reg[13].q tc.adj_s.c_tile_reg[12].q tc.adj_s.c_tile_reg[11].q tc.adj_s.c_tile_reg[10].q tc.adj_s.c_tile_reg[9].q tc.adj_s.c_tile_reg[8].q
vector s_tile_lsb[7:0]  tc.adj_s.c_tile_reg[7].q tc.adj_s.c_tile_reg[6].q tc.adj_s.c_tile_reg[5].q tc.adj_s.c_tile_reg[4].q tc.adj_s.c_tile_reg[3].q tc.adj_s.c_tile_reg[2].q tc.adj_s.c_tile_reg[1].q tc.adj_s.c_tile_reg[0].q
vector t_tile_msb[16:8] tc.adj_t.c_tile_reg[16].q tc.adj_t.c_tile_reg[15].q tc.adj_t.c_tile_reg[14].q tc.adj_t.c_tile_reg[13].q tc.adj_t.c_tile_reg[12].q tc.adj_t.c_tile_reg[11].q tc.adj_t.c_tile_reg[10].q tc.adj_t.c_tile_reg[9].q tc.adj_t.c_tile_reg[8].q
vector t_tile_lsb[7:0]  tc.adj_t.c_tile_reg[7].q tc.adj_t.c_tile_reg[6].q tc.adj_t.c_tile_reg[5].q tc.adj_t.c_tile_reg[4].q tc.adj_t.c_tile_reg[3].q tc.adj_t.c_tile_reg[2].q tc.adj_t.c_tile_reg[1].q tc.adj_t.c_tile_reg[0].q


vector s_tile[16:0] 	s_tile_msb[16:8] s_tile_lsb[7:0]
vector s_tile_diff[9:0] s_tile_diff_msb[9:5] s_tile_diff_lsb[4:0]
vector s_adrs[12:0] 	tc.s_adrs[12:0]
vector s_frac_1d[4:0] 	tc.s_frac[4:0]
vector s_all_zero[3:0] 	tc.s_all_zero[3:0]
vector s_all_one[3:0] 	tc.s_all_one[3:0]

vector t_tile[16:0] 	t_tile_msb[16:8] t_tile_lsb[7:0]
vector t_tile_diff[9:0] t_tile_diff_msb[9:5] t_tile_diff_lsb[4:0]
vector t_adrs[12:0] 	tc.t_adrs[12:0]
vector t_frac_1d[4:0] 	tc.t_frac[4:0]
equiv  tc.mask_en_s 	s_mask_en_1d
equiv  tc.wrap_bit_s 	s_wrap_bit_1d
equiv  tc.mask_en_t 	t_mask_en_1d
equiv  tc.t_all_zero[0] t_all_zero
equiv  tc.t_all_one[0] 	t_all_one
equiv  tc.wrap_bit_t 	t_wrap_bit_1d

# tc_adrs signals
vector tc.a[11:0]
vector tc.b_adder[12:0]
vector tc.c_adder[12:0]
vector tc.d_adder[12:0]
vector tile_tex_size[1:0]
vector tile_tex_type[2:0]

vector a[12:0] 		a_twelve tc.a[11:0]
vector b_adder[12:0] 	tc.b_adder[12:0]
vector c_adder[12:0] 	tc.c_adder[12:0]
vector d_adder[12:0] 	tc.d_adder[12:0]
vector tex_size_1d[1:0] tile_tex_size[1:0]
vector tex_type_1d[2:0] tile_tex_type[2:0]
equiv  tc.copy_1d 	copy_1d
equiv  tc.load_5d 	load_5d
equiv  tc.yuv_tex 	yuv_tex_1d
equiv  tc.flip 		flip
equiv  tc.shift 	shift

# tc_div signals
vector tc.div.rcp2[14:0]
vector tc.div.shft2[3:0]

vector rcp2[14:0] 	tc.div.rcp2[14:0]
vector shft2[3:0] 	tc.div.shft2[3:0]

# tc_frac signals
vector s_frac_ba[7:0]
vector t_frac_ba[7:0]
vector s_frac_rg[7:0]
vector t_frac_rg[7:0]

vector s_frac_ba_out[7:0] s_frac_ba[7:0]
vector t_frac_ba_out[7:0] t_frac_ba[7:0]
vector s_frac_rg_out[7:0] s_frac_rg[7:0]
vector t_frac_rg_out[7:0] t_frac_rg[7:0]
equiv  swap_ba 		 swap_ba_1d
equiv  swap_rg 		 swap_rg_1d

# tc_lod signals
vector l_frac[8:0]
vector tc.l_tile[2:0]

equiv  tc.lod.cycle 	cycle                   
vector l_frac_out[8:0] 	l_frac[8:0]
vector l_tile[2:0] 	tc.l_tile[2:0]
equiv  lod_ge_one 	lod_ge_one_out        
equiv  tc.load_3d 	load_3d             
equiv  tc.load_4d 	load_4d            

# tc_sort signals
vector adrs_a[4:0]
vector adrs_b_ba[4:0]
vector adrs_c[4:0]
vector adrs_d_ba[4:0]
vector adrs_b_rg[4:0]
vector adrs_d_rg[4:0]

vector adrs_bnk0l[7:0]
vector adrs_bnk1l[7:0]
vector adrs_bnk2l[7:0]
vector adrs_bnk3l[7:0]
vector adrs_bnk0h[7:0]
vector adrs_bnk1h[7:0]
vector adrs_bnk2h[7:0]
vector adrs_bnk3h[7:0]
vector adrs_a_1d[4:0] 	 adrs_a[4:0]
vector adrs_b_ba_1d[4:0] adrs_b_ba[4:0]
vector adrs_c_1d[4:0] 	 adrs_c[4:0] 
vector adrs_d_ba_1d[4:0] adrs_d_ba[4:0]
vector adrs_b_rg_1d[4:0] adrs_b_rg[4:0]
vector adrs_d_rg_1d[4:0] adrs_d_rg[4:0]

# tc_tilemem signals
vector tc.tile_tex_type[2:0]
vector tc.tile_tex_size[1:0]
vector tc.line[8:0]
vector tc.tmem_adrs[8:0]
vector palette[3:0]
vector tc.mask_t[3:0]
vector tc.shift_t[3:0]
vector tc.mask_s[3:0]
vector tc.shift_s[3:0]
vector tc.sl[11:0]
vector tc.sh[11:0]
vector tc.tl[11:0]
vector tc.th[11:0]

vector tex_type_2d[2:0]  tc.tile_tex_type[2:0] 
vector tex_size_2d[1:0]  tc.tile_tex_size[1:0]
vector line_2d[8:0] 	 tc.line[8:0]
vector tmem_adrs_2d[8:0] tc.tmem_adrs[8:0]
vector palette_4d[3:0] 	 palette[3:0]
equiv  tc.clamp_t 	 clamp_t_1d
equiv  tc.mir_t  	 mir_t_1d
vector mask_t_1d[3:0] 	 tc.mask_t[3:0]
vector shift_t[3:0] 	 tc.shift_t[3:0]
equiv  tc.clamp_s 	 clamp_s_1d
equiv  tc.mir_s  	 mir_s_1d
vector mask_s_1d[3:0] 	 tc.mask_s[3:0]
vector shift_s[3:0] 	 tc.shift_s[3:0]
vector sl[11:0] 	 tc.sl[11:0]
vector sh[11:0] 	 tc.sh[11:0]
vector tl[11:0] 	 tc.tl[11:0]
vector th[11:0] 	 tc.th[11:0]

# tex signals
vector l_frac[8:0]
vector s_frac_rg[7:0]
vector t_frac_rg[7:0]
vector s_frac_ba[7:0]
vector t_frac_ba[7:0]
vector red_a[8:0]
vector green_a[8:0]
vector blue_a[8:0]
vector alpha_a[8:0]
vector red_b[8:0]
vector green_b[8:0]
vector blue_b[8:0]
vector alpha_b[8:0]
vector red_c[8:0]
vector green_c[8:0]
vector blue_c[8:0]
vector alpha_c[8:0]
vector red_d[8:0]
vector green_d[8:0]
vector blue_d[8:0]
vector alpha_d[8:0]

# tm_load signals
equiv tm.web01_low  web01_low
equiv tm.web23_low  web23_low
equiv tm.web01_high web01_high
equiv tm.web23_high web23_high

# tm_mux signals
vector tm.copy_bus[63:0]

vector copy_bus[63:0] tm.copy_bus[63:0]
vector red_a[8:0]
vector red_b[8:0]
vector red_c[8:0]
vector red_d[8:0]
vector green_a[8:0]
vector green_b[8:0]
vector green_c[8:0]
vector green_d[8:0]
vector blue_a[8:0]
vector blue_b[8:0]
vector blue_c[8:0]
vector blue_d[8:0]
vector alpha_a[8:0]
vector alpha_b[8:0]
vector alpha_c[8:0]
vector alpha_d[8:0]

####################################
# assign static inputs
####################################
inputs l reset_l
inputs l bist_go
inputs l bist_check
inputs l iddq

inputs l st_span
inputs l ncyc
inputs l l[15:0]
inputs l s[15:0]
inputs l t[15:0]
inputs l w[15:0]
inputs l min_level[4:0]
inputs l detail_en
inputs l sharp_en
inputs l lod_en
inputs l persp_en
inputs l copy
inputs l samp_type
inputs l tlut_en
inputs l tlut_type
inputs l max_level[2:0]
inputs l prim_tile[2:0]
inputs l load
inputs l shift_coord
inputs l tile_adrs[2:0]
inputs l tile_data[47:0]
inputs l we_tile_size
inputs l we_tile_attr
inputs l load_dv


####################################
# list signals to be dumped in trace file
####################################

# inputs/bidir
#watch gclk
#watch reset_l
#watch bist_go
#watch bist_check
#watch st_span
#watch ncyc
#watch l
#watch s
#watch t
#watch w
#watch min_level
#watch detail_en       
#watch sharp_en       
#watch lod_en        
#watch persp_en     
#watch copy        
#watch samp_type  
#watch tlut_en   
#watch tlut_type
#watch max_level
#watch prim_tile
#watch load                 
#watch shift_coord         
#watch tile_adrs
#watch tile_data
#watch we_tile_size     
#watch we_tile_attr    
#watch copy_load
#watch copy_load_oe       
#watch load_dv           

# tc_adj outputs
#watch s_tile
#watch s_tile_diff
#watch s_adrs
#watch s_frac_1d
#watch s_mask_en_1d         
#watch s_all_zero
#watch s_all_one
#watch s_wrap_bit_1d     
#watch t_tile
#watch t_tile_diff
#watch t_adrs
#watch t_frac_1d
#watch t_mask_en_1d         
#watch t_all_zero          
#watch t_all_one          
#watch t_wrap_bit_1d     

# tc_adrs outputs
#watch a
#watch b_adder
#watch c_adder
#watch d_adder
#watch shift       
#watch flip       
#watch odd_t     
#watch yuv_tex_1d     
#watch load_5d          
#watch copy_1d         
#watch tex_type_1d
#watch tex_size_1d
#watch a_three        

# tc_div outputs
#watch s_tile
#watch t_tile
#watch rcp2
#watch shft2

# tc_frac outputs
#watch s_frac_ba_2d
#watch t_frac_ba_2d
#watch s_frac_rg_2d
#watch t_frac_rg_2d
#watch swap_ba_1d
#watch swap_rg_1d

# tc_lod outputs
#watch cycle
#watch l_frac_7d
#watch l_tile
#watch lod_ge_one_7d
#watch load_3d
#watch load_4d

# tc_sort outputs
#watch adrs_bnk0l
#watch adrs_bnk1l
#watch adrs_bnk2l
#watch adrs_bnk3l
#watch adrs_bnk0h
#watch adrs_bnk1h
#watch adrs_bnk2h
#watch adrs_bnk3h
#watch adrs_a_1d
#watch adrs_b_ba_1d
#watch adrs_c_1d
#watch adrs_d_ba_1d
#watch adrs_b_rg_1d
#watch adrs_d_rg_1d

# tc_tilemem outputs
#watch tex_type_2d
#watch tex_size_2d
#watch line_2d
#watch tmem_adrs_2d
#watch palette_4d
#watch clamp_t_1d
#watch mir_t_1d
#watch mask_t_1d
#watch shift_t
#watch clamp_s_1d
#watch mir_s_1d
#watch mask_s_1d
#watch shift_s
#watch sl
#watch sh
#watch tl
#watch th

# tex outputs
#watch l_frac
#watch lod_ge_one
#watch s_frac_rg
#watch t_frac_rg
#watch s_frac_ba
#watch t_frac_ba
#watch red_a
#watch green_a
#watch blue_a
#watch alpha_a
#watch red_b
#watch green_b
#watch blue_b
#watch alpha_b
#watch red_c
#watch green_c
#watch blue_c
#watch alpha_c
#watch red_d
#watch green_d
#watch blue_d
#watch alpha_d

# tm_load outputs
#watch web01_low
#watch web23_low
#watch web01_high
#watch web23_high

# tm_mux outputs
#watch copy_bus
#watch red_a
#watch red_b
#watch red_c
#watch red_d
#watch green_a
#watch green_b
#watch green_c
#watch green_d
#watch blue_a
#watch blue_b
#watch blue_c
#watch blue_d
#watch alpha_a
#watch alpha_b
#watch alpha_c
#watch alpha_d

# ram_bist_tmem outputs
#watch bist_done
#watch bist0_fail
#watch bist1_fail
#watch bist2_fail
#watch bist3_fail
#watch bist4_fail
#watch bist5_fail
#watch bist6_fail
#watch bist7_fail

#tmem debug
#watch tm.low_half.bnk0.pcg
#watch tm.low_half.bnk0.csb
#vector tm.low_half.bnk0.a[7:0]
#watch tm.low_half.bnk0.a
#vector tm.low_half.bnk0.web[1:0]
#watch tm.low_half.bnk0.web
#vector tm.low_half.bnk0.di[15:0]
#watch tm.low_half.bnk0.di
#vector tm.low_half.bnk0.dout[15:0]
#watch tm.low_half.bnk0.dout

#tilemem debug

#vector tc.tilemem.tile_adrs[2:0]
#vector tc.tilemem.tile_data[47:0]
#watch tc.tilemem.tile_adrs
#watch tc.tilemem.tile_data
#watch tc.tilemem.we_tile_size
#watch tc.tilemem.we_tile_attr
####################################
# open trc file
####################################
output (only) [trc]$1

####################################
# load sim file
####################################
load [sim]$1

####################################
# close trc file
####################################
output .

####################################
# display % of nodes toggled
####################################
toggles (totals)

q
q
EOF