top_level.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: top_level.v,v 1.1.1.1 2002/05/02 03:29:06 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: top_level
// description: Top Level Driver
//
// designer: Tony DeLaurier
// date: 8/8/94
//
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps //1unit = 0.01ns
module top_level();
wire gclk; // RDP gated clock
wire st_span; // start span
wire ncyc; // 0: 1-cycle mode, 1: 2-cycle mode
// pixel data
wire [15:0] l; // level of detail
wire [15:0] s; // persp. divided texture image coord.
wire [15:0] t; // persp. divided texture image coord.
wire [15:0] w; // inverse normalized depth
// attribute data
wire [4:0] min_level; // minimum lod fraction clamp
wire detail_en; // enable detailed texture
wire sharp_en; // enable sharpened texture
wire lod_en; // use lod in tile indices determination
wire persp_en; // enable perspective correction
wire copy; // copy mode enabled
wire samp_type; // filter enabled
wire tlut_en; // enable texture lookup table
wire tlut_type; // tlut type
// primitive data
wire [2:0] max_level; // number of mipmaps -1 or -2
wire [2:0] prim_tile; // base tile index of primitive
wire load; // load_tile, load_block or load_tlut
wire shift_coord; // treat coord as 12.3 instead of 10.5
// from command interface unit
wire [2:0] tile_adrs; // tile write address
wire [47:0] tile_data; // tile wire data
wire we_tile_size; // write enable for tile size data
wire we_tile_attr; // write enable for tile attribute data
// to color combine unit
wire [8:0] l_frac; // lod fraction for 3rd-axis interpolation
wire lod_ge_one; // lod >= 1
// to / from memspan unit
wire [63:0] copy_load; // bidirectional copy / load bus
wire load_dv; // valid load data on copy_load bus
// to texture filter unit
wire [8:0] red_a; // texel a, red / u channel
wire [8:0] green_a; // texel a, green / v channel
wire [8:0] blue_a; // texel a, blue / y channel
wire [8:0] alpha_a; // texel a, alpha / y channel
wire [8:0] red_b; // texel b, red / u channel
wire [8:0] green_b; // texel b, green / v channel
wire [8:0] blue_b; // texel b, blue / y channel
wire [8:0] alpha_b; // texel b, alpha / y channel
wire [8:0] red_c; // texel c, red / u channel
wire [8:0] green_c; // texel c, green / v channel
wire [8:0] blue_c; // texel c, blue / y channel
wire [8:0] alpha_c; // texel c, alpha / y channel
wire [8:0] red_d; // texel d, red / u channel
wire [8:0] green_d; // texel d, green / v channel
wire [8:0] blue_d; // texel d, blue / y channel
wire [8:0] alpha_d; // texel d, alpha / y channel
wire [7:0] s_frac_rg; // s interp fraction to filter (RG)
wire [7:0] t_frac_rg; // t interp fraction to filter (RG)
wire [7:0] s_frac_ba; // s interp fraction to filter (BA)
wire [7:0] t_frac_ba; // t interp fraction to filter (BA)
// other
wire bist_done; // bist done
wire bist0_fail; // mem test fail flag (active high) (bnk0)
wire bist1_fail; // mem test fail flag (active high) (bnk1)
wire bist2_fail; // mem test fail flag (active high) (bnk2)
wire bist3_fail; // mem test fail flag (active high) (bnk3)
wire bist4_fail; // mem test fail flag (active high) (bnk4)
wire bist5_fail; // mem test fail flag (active high) (bnk5)
wire bist6_fail; // mem test fail flag (active high) (bnk6)
wire bist7_fail; // mem test fail flag (active high) (bnk7)
// instance driver
driver driver(.st_span(st_span), .ncyc(ncyc), .l(l), .s(s), .t(t), .w(w),
.min_level(min_level), .detail_en(detail_en),
.sharp_en(sharp_en), .lod_en(lod_en), .persp_en(persp_en),
.copy(copy), .samp_type(samp_type), .tlut_en(tlut_en),
.tlut_type(tlut_type), .max_level(max_level),
.prim_tile(prim_tile), .load(load), .shift_coord(shift_coord),
.tile_adrs(tile_adrs), .tile_data(tile_data),
.we_tile_size(we_tile_size), .we_tile_attr(we_tile_attr),
.load_dv(load_dv),
.copy_load(copy_load), .gclk(gclk),
.load_4d(tex.tc.load_4d), .load_3d(tex.tc.load_3d),
.lod_ge_one_out(lod_ge_one), .l_tile(tex.tc.l_tile),
.l_frac_out(l_frac), .cycle(tex.tc.lod.cycle),
.copy_load_oe(tex.tm.copy_load_oe));
// instance tex unit
tex tex (.gclk(gclk), .reset_l(1'b0), .bist_go(1'b0), .bist_check(1'b0), .iddq(1'b0),
.st_span(st_span), .ncyc(ncyc), .l(l),
.s(s), .t(t), .w(w), .min_level(min_level), .detail_en(detail_en),
.sharp_en(sharp_en), .lod_en(lod_en), .persp_en(persp_en),
.copy(copy), .samp_type(samp_type), .tlut_en(tlut_en),
.tlut_type(tlut_type), .max_level(max_level), .prim_tile(prim_tile),
.load(load), .shift_coord(shift_coord), .tile_adrs(tile_adrs),
.tile_data(tile_data), .we_tile_size(we_tile_size),
.we_tile_attr(we_tile_attr),
.l_frac(l_frac), .lod_ge_one(lod_ge_one),
.s_frac_rg(s_frac_rg), .t_frac_rg(t_frac_rg), .s_frac_ba(s_frac_ba),
.t_frac_ba(t_frac_ba), .red_a(red_a), .green_a(green_a),
.blue_a(blue_a), .alpha_a(alpha_a), .red_b(red_b),
.green_b(green_b), .blue_b(blue_b), .alpha_b(alpha_b),
.red_c(red_c), .green_c(green_c), .blue_c(blue_c),
.alpha_c(alpha_c), .red_d(red_d), .green_d(green_d),
.blue_d(blue_d), .alpha_d(alpha_d), .copy_load(copy_load),
.load_dv(load_dv), .bist_done(bist_done), .bist0_fail(bist0_fail),
.bist1_fail(bist1_fail), .bist2_fail(bist2_fail), .bist3_fail(bist3_fail),
.bist4_fail(bist4_fail), .bist5_fail(bist5_fail), .bist6_fail(bist6_fail),
.bist7_fail(bist7_fail));
// kill simulation when tabular file read
always @(driver.EndVectors)
$finish;
// dump file
initial
begin
$dumpvars;
end
endmodule // top_level