Makefile
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#!smake -J 5
PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs
#
# Directories
#
TCTM = ../..
INDATA = ../../InData
RTLOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/hw/chip/rcp/tc/src \
-y $(PRDEPTH)/hw/chip/rcp/tm/src \
-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw/chip/lib/verilog/ram \
+libext+.v+.vzd \
+incdir+$(PRDEPTH)/hw/chip/rcp/inc
SYNOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/hw/chip/rcp/tc/syn \
-y $(PRDEPTH)/hw/chip/rcp/tm/syn \
-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw/chip/lib/verilog/ram \
+libext+.v+.vzd+.vsyn
LDIRT = driver*.v *.mem *.out vcs.log *.dump $(TMPDIR)/$(USER)_tm_load021 $(TMPDIR)/$(USER)_tm_load022 $(TMPDIR)/$(USER)_tm_load021_syn $(TMPDIR)/$(USER)_tm_load022_syn *.tab simv*
RTESTS = tm_load021 tm_load022
STESTS = tm_load021_syn tm_load022_syn
FAST = fast021 fast022
ERROR = \
@if grep "ERROR IN SIMULATION" FILE ; \
then \
echo ""; \
else \
echo "NO ERRORS IN SIMULATION"; \
fi
default: $(RTESTS)
stests: $(STESTS)
include $(PRDEPTH)/PRrules
.mem.out:
$(RTESTS): simv021 simv022
$(STESTS): simv021_syn simv022_syn
tm_load021.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp011.tab $@.base.Z
(cd ../..; make test021)
/usr/bsd/uncompress $@.base.Z
cmp $@ $@.base
/usr/bsd/compress $@.base
tm_load022.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp011.tab $(INDATA)/inp012.tab $@.base.Z
(cd ../..; make test022)
/usr/bsd/uncompress $@.base.Z
cmp $@ $@.base
/usr/bsd/compress $@.base
driver021.v: tm_load021.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 tm_load021.tab > driver021.v
driver022.v: tm_load022.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 tm_load022.tab > driver022.v
simv021: top_level.v driver021.v tm_load021.mem $(_FORCE)
$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv021 -Mdir="$(TMPDIR)/$(USER)_tm_load021" top_level.v driver021.v
@ if [ "$(DUMP)" ]; \
then \
(echo "simv021 +mem=tm_load021.mem > simv021.out"; simv021 -vcd verilog021.dump +mem=tm_load021.mem > simv021.out;) \
else \
(echo "simv021 +mem=tm_load021.mem > simv021.out"; simv021 +mem=tm_load021.mem +vcs+dumpvarsoff > simv021.out;) \
fi
$(ERROR:FILE=simv021.out)
$(LOG_ERROR)
simv022: top_level.v driver022.v tm_load022.mem $(_FORCE)
$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv022 -Mdir="$(TMPDIR)/$(USER)_tm_load022" top_level.v driver022.v
@ if [ "$(DUMP)" ]; \
then \
(echo "simv022 +mem=tm_load022.mem > simv022.out"; simv022 -vcd /usr/tmp/tonyd/verilog022.dump +mem=tm_load022.mem > simv022.out;) \
else \
(echo "simv022 +mem=tm_load022.mem > simv022.out"; simv022 +mem=tm_load022.mem +vcs+dumpvarsoff > simv022.out;) \
fi
$(ERROR:FILE=simv022.out)
$(LOG_ERROR)
simv021_syn: top_level.vsyn driver021.v tm_load021.mem $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
-Mdir="$(TMPDIR)/$(USER)_tm_load021_syn" top_level.vsyn driver021.v
@ if [ "$(DUMP)" ]; \
then \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tm_load021.mem > $@.out"; $@ -vcd verilog021_syn.dump +mem=tm_load021.mem > $@.out;) \
else \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tm_load021.mem > $@.out"; $@ +mem=tm_load021.mem +vcs+dumpvarsoff > $@.out;) \
fi
$(ERROR:FILE=simv021_syn.out)
$(LOG_ERROR)
simv022_syn: top_level.vsyn driver022.v tm_load022.mem $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so $(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
-Mdir="$(TMPDIR)/$(USER)_tm_load022_syn" top_level.vsyn driver022.v
@ if [ "$(DUMP)" ]; \
then \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tm_load022.mem > $@.out"; $@ -vcd /usr/tmp/tonyd/verilog022_syn.dump +mem=tm_load022.mem > $@.out;) \
else \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tm_load022.mem > $@.out"; $@ +mem=tm_load022.mem +vcs+dumpvarsoff > $@.out;) \
fi
$(ERROR:FILE=simv022_syn.out)
$(LOG_ERROR)
fast: $(FAST)
fast021: tm_load021.mem
simv021 +mem=$? | tee $*.out
fast022: tm_load022.mem
simv022 +mem=$? | tee $*.out