Makefile 3.81 KB
#!smake -J 3
#
#

PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs

LVCSOPTS     =	-y .                                                    \
		+incdir+$(PRDEPTH)/hw/chip/rcp/inc

OLDOPTS	     =	-y $(PRDEPTH)/hw/chip/rcp/vi/src                        \
		-y $(PRDEPTH)/hw/chip/rcp/rdp/src                       \
		-y $(PRDEPTH)/hw/chip/lib/verilog/sc                    \
		-y $(PRDEPTH)/hw/chip/lib/verilog/ram                   \
		-v $(PRDEPTH)/hw/chip/lib/verilog/udp/compass_udps.v    \
		+libext+.v+.vzd                                         \
		-P $(ROOT)/PR/rdpsim/test/vi/OutData/vi_lerp/Pli/pli.tab \
		$(ROOT)/PR/rdpsim/test/vi/OutData/vi_lerp/Pli/libpli.a   \

RTLOPTS	     =	-y $(PRDEPTH)/hw/chip/rcp/vi/src                        \
		-y $(PRDEPTH)/hw/chip/rcp/rdp/src                       \
		-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell               \
		-y $(PRDEPTH)/hw/chip/lib/verilog/ram                   \
		+libext+.v                                              \
		-P $(ROOT)/PR/rdpsim/test/vi/OutData/vi_lerp/Pli/pli.tab \
		$(ROOT)/PR/rdpsim/test/vi/OutData/vi_lerp/Pli/libpli.a   \

SYNOPTS	     =	-y $(PRDEPTH)/hw/chip/rcp/vi/syn                        \
		-y $(PRDEPTH)/hw/chip/rcp/rdp/syn                       \
		-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell               \
		-y $(PRDEPTH)/hw/chip/lib/verilog/ram                   \
		+libext+.v+.vsyn                                        \
		-P $(ROOT)/PR/rdpsim/test/vi/OutData/vi_lerp/Pli/pli.tab \
		$(ROOT)/PR/rdpsim/test/vi/OutData/vi_lerp/Pli/libpli.a   \

LDIRT = driver*.v *.mem *.out vcs.log *.dump vi_lerp0?? *.tab simv* inp??? Pli/*.o Pli/*.a checklerp rsimv* ssimv* rtlcsrc* syncsrc* 

SUBDIRS	= Pli

HDR	= $(ROOT)/PR/include

LCINCS	= -I. \
	-I$(HDR) \
	-I$(ROOT) 

include $(PRDEPTH)/PRrules

.mem.out: 

ERROR = \
	@if  grep "ERROR" FILE ;	\
	then	echo "";    \
	else					\
		echo "NO ERRORS IN SIMULATION";	\
	fi 

RTESTS = rsimv000
STESTS = ssimv000
OTESTS = simv000

default: checklerp $(RTESTS)

stests: $(STESTS)

otests: $(OTESTS)


$(PLI)/libpli.a: $(_FORCE)
	(cd Pli; make ; cd ..)

checklerp: checklerp.c vivl.c
	$(CC) $(LCINCS) -o $@ checklerp.c

inp000: inp000.c
	$(CC) $(LCINCS) -o $@ $? -lm

vi_lerp000.tab: inp000
	inp000 > vi_lerp000.tab

driver000.v: vi_lerp000.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 vi_lerp000.tab > driver000.v

simv000: top_level.v driver000.v display.v vi_lerp000.mem $(PLI)/libpli.a checklerp
	$(VCS) $(VCSOPTS) $(OLDOPTS) -o simv000 -Mdir="vi_lerp000" top_level.v driver000.v 
	@ if [ "$(DUMP)" ]; \
	then (echo "simv -dump" ; simv000 -vcd verilog000.dump +out=test000.out +dump=yes +mem=vi_lerp000.mem > simv000.out) \
	else (echo "simv -nodump" ; simv000 +mem=vi_lerp000.mem +out=test000.out +vcs+dumpvarsoff > simv000.out) \
	fi 
	checklerp test000.out | tee checklerp000.out
	$(ERROR:FILE=checklerp000.out)

rsimv000: top_level.v driver000.v display.v vi_lerp000.mem $(PLI)/libpli.a checklerp
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o rsimv000 -Mdir="vi_lerp000" top_level.v driver000.v 
	@ if [ "$(DUMP)" ]; \
	then (echo "rsimv -dump" ; rsimv000 -vcd rverilog000.dump +out=rtest000.out +dump=yes +mem=vi_lerp000.mem > rsimv000.out) \
	else (echo "rsimv -nodump" ; rsimv000 +mem=vi_lerp000.mem +out=rtest000.out +vcs+dumpvarsoff > rsimv000.out) \
	fi 
	checklerp rtest000.out | tee rchecklerp000.out
	$(ERROR:FILE=rchecklerp000.out)


ssimv000: top_level.v driver000.v display.v vi_lerp000.mem $(PLI)/libpli.a checklerp
	$(VCS) $(VCSOPTS) $(SYNOPTS) -o ssimv000 -Mdir="vi_lerp000" top_level.v driver000.v 
	@ if [ "$(DUMP)" ]; \
	then (echo "ssimv -dump" ; ssimv000 -vcd sverilog000.dump +out=stest000.out +dump=yes +mem=vi_lerp000.mem > ssimv000.out) \
	else (echo "ssimv -nodump" ; ssimv000 +mem=vi_lerp000.mem +out=stest000.out +vcs+dumpvarsoff > ssimv000.out) \
	fi 
	checklerp stest000.out | tee schecklerp000.out
	$(ERROR:FILE=schecklerp000.out)