driver.v
3.59 KB
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`timescale 10ps / 10ps //1unit = 0.01ns
module driver(reset_l, ri_cbus_read_enable, ri_cbus_write_enable,
cbus_command, ri_read_grant, bus_clk,
dma_ready, dma_start, dma_last, ri_read_request,
sp_dbus_read_enable, mi_dbus_read_enable, span_dbus_read_enable,
sp_dbus_write_enable, mi_dbus_write_enable,
pi_dbus_write_enable, si_dbus_write_enable,
span_dbus_write_enable,
cbus_data, dbus_data, ebus_data,
clock,
c_ctl_ld);
`include "rcp.vh"
`include "rdram.vh"
`include "driver_tasks.vh"
// driver outputs (ri_test inputs)
output reset_l;
output ri_cbus_read_enable;
output ri_cbus_write_enable;
output [CBUS_COMMAND_SIZE-1:0] cbus_command;
output ri_read_grant;
output bus_clk;
// driver inputs (ri_test outputs)
input dma_ready;
input dma_start;
input dma_last;
input ri_read_request;
input sp_dbus_read_enable;
input mi_dbus_read_enable;
input span_dbus_read_enable;
input sp_dbus_write_enable;
input mi_dbus_write_enable;
input pi_dbus_write_enable;
input si_dbus_write_enable;
input span_dbus_write_enable;
inout [CBUS_DATA_SIZE-1:0] cbus_data;
inout [DBUS_DATA_SIZE-1:0] dbus_data;
inout [EBUS_DATA_SIZE-1:0] ebus_data;
input clock;
input c_ctl_ld;
// registers
reg bus_clk;
reg reset_l;
reg ri_cbus_read_enable;
reg ri_cbus_write_enable;
reg [CBUS_COMMAND_SIZE-1:0] cbus_command;
reg [CBUS_DATA_SIZE-1:0] cbus_data_reg;
reg [DBUS_DATA_SIZE-1:0] dbus_data_out, dbus_data_reg;
reg [EBUS_DATA_SIZE-1:0] ebus_data_out, ebus_data_reg;
reg ri_read_grant;
assign cbus_data = cbus_data_reg;
always @(posedge clock)
begin
dbus_data_reg <= mi_dbus_read_enable ? dbus_data : dbus_data_out;
ebus_data_reg <= mi_dbus_read_enable ? ebus_data : ebus_data_out;
end
dbus_driver dbus_driver_0(dbus_data_reg, mi_dbus_write_enable, dbus_data);
ebus_driver ebus_driver_0(ebus_data_reg, mi_dbus_write_enable, ebus_data);
// internal variables
integer errors;
//
// Clear x's out of the rac clock generator
//
initial
begin
force ri_test_0.syn_clk_in = LOW;
wait (ri_test_0.syn_clk);
release ri_test_0.syn_clk_in;
end
//
// Generate Clock
//
always
begin
bus_clk = 1;
#200;
bus_clk = 0;
#200;
end
initial
begin
reset_l <= 0;
cbus_command <= 0;
ri_read_grant <= 0;
repeat (10) @(posedge clock);
reset_l <= 1;
ri_cbus_read_enable <= 1;
ri_cbus_write_enable <= 0;
ri_read_grant <= 0;
initialize_dram;
errors = 0;
if ($test$plusargs("dump")) $dumpvars;
if ($test$plusargs("test000")) test000;
if ($test$plusargs("test001")) test001;
if ($test$plusargs("test002")) test002;
if ($test$plusargs("test003")) test003;
if ($test$plusargs("test004")) test004;
if ($test$plusargs("test005")) test005;
if ($test$plusargs("test006")) test006;
if ($test$plusargs("test007")) test007;
if ($test$plusargs("test008")) test008;
if ($test$plusargs("test009")) test009;
if ($test$plusargs("test010")) test010;
if ($test$plusargs("test011")) test011;
if ($test$plusargs("test012")) test012;
if ($test$plusargs("test013")) test013;
if ($test$plusargs("test014")) test014;
if ($test$plusargs("test015")) test015;
$write("number of errors: %d\n", errors);
$finish;
end
`include "driver_tasks.v"
`include "test000.v"
`include "test001.v"
`include "test002.v"
`include "test003.v"
`include "test004.v"
`include "test005.v"
`include "test006.v"
`include "test007.v"
`include "test008.v"
`include "test009.v"
`include "test010.v"
`include "test011.v"
`include "test012.v"
`include "test013.v"
`include "test014.v"
`include "test015.v"
endmodule