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/************************************************************************
DMA WRITE TESTS: File #4
************************************************************************/
.word 0x12A343E2
.word 0x425943D4
.word 0x6AF747BB
.word 0x38463A6B
.word 0x751D7C4E
.word 0x52C74DBA
.word 0x24336D4A
.word 0x621C431A
.word 0x1C21797B
.word 0x478C116C
.word 0x573E450A
.word 0x60EE53B1
.word 0x7AC3137A
.word 0x20F44968
.word 0x05F0455E
.word 0x603B00AB
.word 0x480075DA
.word 0x33130608
.word 0x48CD73E1
.word 0x500E3620
.word 0x10431328
.word 0x534A0D02
.word 0x788610EC
.word 0x6A7E0F45
.word 0x76E30869
.word 0x35C728E7
.word 0x07783315
.word 0x69301DE9
.word 0x27A270A1
.word 0x7B0368A6
.word 0x0B2952AD
.word 0x6AD221F7
.word 0x782D284D
.word 0x6D444F08
.word 0x75D04540
.word 0x08A130F9
.word 0x39A100EA
.word 0x6E1B7234
.word 0x7FCB2917
.word 0x1BE24D91
.word 0x3A02646E
.word 0x13E60B2B
.word 0x412940B7
.word 0x336A6F00
.word 0x75C368CC
.word 0x774D754B
.word 0x7B203E61
.word 0x391778A1
.word 0x79435373
.word 0x30C61DCD
.word 0x11967F91
.word 0x4757216C
.word 0x724D0CCE
.word 0x06136349
.word 0x349A3881
.word 0x2E9E4B76
.word 0x719503C3
.word 0x47C1652F
.word 0x39E90FA6
.word 0x2AF24B6E
.word 0x5C400135
.word 0x5EA9434D
.word 0x266C2930
.word 0x49622020
.word 0x0D5A6B84
.word 0x09704D4E
.word 0x67B7228C
.word 0x7D8819F4
.word 0x275F7A0A
.word 0x4A092238
.word 0x3D8A7DE4
.word 0x670C726D
.word 0x15B5589E
.word 0x03303FEB
.word 0x53527D9B
.word 0x472253AC
.word 0x3E2F3B13
.word 0x45EF02A7
.word 0x09A66FD3
.word 0x26094FED
.word 0x628A60B8
.word 0x4F1A1484
.word 0x6FCC69E9
.word 0x288C4906
.word 0x31F107D7
.word 0x34D54CF9
.word 0x6D3473F6
.word 0x158347ED
.word 0x0A7A5138
.word 0x440B0058
.word 0x1AFA244E
.word 0x0B514431
.word 0x6AA9139E
.word 0x0DF73F4F
.word 0x4D662B03
.word 0x65665B7F
.word 0x12EA1F47
.word 0x259D0666
.word 0x4D6D4D60
.word 0x51BC791C
.word 0x5719716E
.word 0x0D4F5D85
.word 0x42305170
.word 0x165B6D6F
.word 0x1FFC57CA
.word 0x542B676E
.word 0x4A7A5977
.word 0x06D77576
.word 0x1CC5040D
.word 0x6399613D
.word 0x46442F76
.word 0x29CF324E
.word 0x24930F68
.word 0x7CCF11ED
.word 0x503200A9
.word 0x0E6F10AE
.word 0x47F06E05
.word 0x664F29D4
.word 0x6715090A
.word 0x51ED206A
.word 0x1252528A
.word 0x49661223
.word 0x47692ECE
.word 0x550D5BF3
.word 0x7B9C019A
.word 0x3FAD2C69
.word 0x74D70DE5
.word 0x219E5FD3
.word 0x099C1555
.word 0x108A0210
.word 0x73B2737C
.word 0x7FFD1233
.word 0x218D30D5
.word 0x1EAE63DD
.word 0x327C497C
.word 0x3C8F3A57
.word 0x099523B1
.word 0x05967971
.word 0x2360720B
.word 0x1D49081E
.word 0x1A467D7C
.word 0x670C40CC
.word 0x05B81308
.word 0x072B0B85
.word 0x201F1144
.word 0x68A57DC7
.word 0x5F865191
.word 0x53BE1C23
.word 0x6D096916
.word 0x61431998
.word 0x26FD7D7E
.word 0x569B30AD
.word 0x19DD2977
.word 0x36927250
.word 0x1BF72CE6
.word 0x12E52671
.word 0x77DB64EA
.word 0x6A8D1A5E
.word 0x517E4797
.word 0x20CC78DD
.word 0x32325F6F
.word 0x58F8080B
.word 0x674602A0
.word 0x430A68F7
.word 0x1F7C4200
.word 0x24E634FE
.word 0x732F4BC8
.word 0x2C6814E4
.word 0x43413E14
.word 0x56332DB7
.word 0x1AC62516
.word 0x75387F64
.word 0x7F72211D
.word 0x27081116
.word 0x5CC3704A
.word 0x40DA0752
.word 0x75ED580C
.word 0x015C7FD3
.word 0x0A8A2A60
.word 0x133A4F27
.word 0x19FE62CA
.word 0x2C6F7C06
.word 0x71AB1712
.word 0x564E1475
.word 0x71DA37BF
.word 0x2A4F389F
.word 0x35645C55
.word 0x0F9A776E
.word 0x0824174E
.word 0x455558EC
.word 0x581C0DD9
.word 0x45AE325D
.word 0x0D6A4F54
.word 0x4DA72018
.word 0x74E9288B
.word 0x15A54129
.word 0x29A66EAE
.word 0x06B610A8
.word 0x29097E14
.word 0x78A578D8
.word 0x7DC068B2
.word 0x44C07BFF
.word 0x2D6A105A
.word 0x39640F07
.word 0x550828B3
.word 0x3A4D01D9
.word 0x20245CFC
.word 0x199F1175
.word 0x06BF1580
.word 0x75B37FD1
.word 0x7DFB18D8
.word 0x27A34D77
.word 0x078D04E3
.word 0x0E9470DD
.word 0x4BE15B86
.word 0x43C62783
.word 0x2B0A1F24
.word 0x035C3CCF
.word 0x70703ADC
.word 0x55EC62A8
.word 0x15383285
.word 0x46C677D4
.word 0x3D71566A
.word 0x33055812
.word 0x5C0476C6
.word 0x7D5711F7
.word 0x295A52FE
.word 0x328C1E89
.word 0x58CB40A1
.word 0x6AE0769D
.word 0x38CA4620
.word 0x740821F1
.word 0x29D1254D
.word 0x0FFD1C08
.word 0x180D1195
.word 0x548C2AC9
.word 0x63C90DFC
.word 0x779A02D6
.word 0x649C2EDD
.word 0x143855AD
.word 0x73533B5F
.word 0x346B2581
.word 0x269C6AB6
.word 0x2BB87AD6
.word 0x2E77391F
.word 0x0E7157DF
.word 0x7A5D1099
.word 0x51C20597
.word 0x162D4164
.word 0x607B16A1
.word 0x69DA063B
.word 0x309B3BE0
.word 0x47D61051
.word 0x25A046D6
.word 0x763D570C
.word 0x4B9175BE
.word 0x1EC22783
.word 0x36C76568
.word 0x515A2FB9
.word 0x147F44D7
.word 0x05AA0197
.word 0x3821269B
.word 0x473149AB
.word 0x314E0BEF
.word 0x783535A3
.word 0x36AC0593
.word 0x576F4687
.word 0x71710668
.word 0x34750ABA
.word 0x75B043CD
.word 0x7EEB7BAE
.word 0x73663FBB
.word 0x1C6A7B6A
.word 0x6C4458A2
.word 0x312B2DBD
.word 0x7A3A7B03
.word 0x477C293F
.word 0x72C850CA
.word 0x01DF3C0D
.word 0x73040A71
.word 0x44024040
.word 0x206A1DD5
.word 0x7E633C32
.word 0x2A6616D6
.word 0x08BF4A70
.word 0x58A355B2
.word 0x373F057D
.word 0x3211571F
.word 0x1662734C
.word 0x08B8622A
.word 0x79A92C7B
.word 0x764037D2
.word 0x49043B51
.word 0x153C2063
.word 0x38FF6E76
.word 0x033A7294
.word 0x59AC1B75
.word 0x778B7060
.word 0x284F0CF2
.word 0x7AD315A4
.word 0x0FCC18AA
.word 0x0B4F347D
.word 0x03D1192F
.word 0x39E97B5F
.word 0x22C34761
.word 0x0BFD40F6
.word 0x0A6A2FAC
.word 0x2DE931BD
.word 0x4B5B3F03
.word 0x42573B5F
.word 0x272923A0
.word 0x5A4A51D0
.word 0x054A7D78
.word 0x61E96A2B
.word 0x4ACB1A80
.word 0x0E0E474A
.word 0x00B43AA2
.word 0x168E7427
.word 0x7539177E
.word 0x494607F5
.word 0x43A52BE1
.word 0x41EA0FFE
.word 0x6F067706
.word 0x528D3B3B
.word 0x7B99378F
.word 0x68F023B5
.word 0x32F45A41
.word 0x7C8A519E
.word 0x7EF61882
.word 0x515B542E
.word 0x076E0294
.word 0x1B710C3F
.word 0x7E8E718F
.word 0x4F3704A7
.word 0x480E1D20
.word 0x2A817459
.word 0x671F5104
.word 0x4258463B
.word 0x5F167E42
.word 0x218542C5
.word 0x72D5242B
.word 0x43DF375D
.word 0x6EF94D12
.word 0x7A543775
.word 0x6AC51ACC
.word 0x03BA5362
.word 0x2BD11EE6
.word 0x665360FB
.word 0x18727AA9
.word 0x562231F6
.word 0x64E902CE
.word 0x33F05402
.word 0x674B6301
.word 0x711D36A4
.word 0x3E327D18
.word 0x642752D2
.word 0x36280010
.word 0x59FC3050
.word 0x19D072CB
.word 0x700064CE
.word 0x58D22E8C
.word 0x02DC68BE
.word 0x318C052E
.word 0x3E0C5DF7
.word 0x497A0F27
.word 0x1827240B
.word 0x60615D41
.word 0x47ED5668
.word 0x0A3F0A12
.word 0x7E131031
.word 0x1BF26740
.word 0x6FCD11DA
.word 0x36AA4276
.word 0x7E1F2486
.word 0x1E107E25
.word 0x05E45720
.word 0x453379FB
.word 0x249B713B
.word 0x3E370724
.word 0x7DF537AA
.word 0x78BC6443
.word 0x4E1F5EDF
.word 0x7B0F7D2F
.word 0x54CF4704
.word 0x02136A6D
.word 0x65105DDB
.word 0x33ED6C72
.word 0x25CE4256
.word 0x51735E95
.word 0x4F2105F6
.word 0x12525DD6
.word 0x705A27E4
.word 0x18011F51
.word 0x0ACE25D0
.word 0x23693280
.word 0x0D643E8D
.word 0x79512B34
.word 0x7CE14269
.word 0x218B6F51
.word 0x54EE0D4E
.word 0x6CE0244C
.word 0x6DEE069A
.word 0x6DBC7865
.word 0x738242BE
.word 0x4F9A43A5
.word 0x37D92298
.word 0x392E3C97
.word 0x6FB80C91
.word 0x25543CC6
.word 0x234D1B76
.word 0x5EBB50FA
.word 0x5FB35F17
.word 0x0A501131
.word 0x75440AA2
.word 0x6C6D7C5F
.word 0x4EA32CBC
.word 0x54BE53E5
.word 0x2C844D64
.word 0x5CF732D3
.word 0x52420D88
.word 0x66385CDE
.word 0x6F1F2465
.word 0x013B0120
.word 0x5058569F
.word 0x2D436C92
.word 0x27F04324
.word 0x19C46849
.word 0x743921C1
.word 0x56D33F73
.word 0x54224F80
.word 0x204C2911
.word 0x544444C9
.word 0x2FC51172
.word 0x00AB5134
.word 0x41367F73
.word 0x4764392F
.word 0x36641178
.word 0x77CB1154
.word 0x05124E29
.word 0x6A917387
.word 0x5BE744ED
.word 0x1E9069D3
.word 0x2A1E3A27
.word 0x564E2B02
.word 0x75F05B33
.word 0x025304FE
.word 0x2DC1361F
.word 0x042B10EA
.word 0x600C7129
.word 0x16390D00
.word 0x06107DFD
.word 0x64427829
.word 0x4D3844AB
.word 0x20B54B5D
.word 0x0B4B026A
.word 0x22BC6CC1
.word 0x4958580E
.word 0x5903387A
.word 0x115F444B
.word 0x1D4B3B52
.word 0x6ABF05A7
.word 0x34AD7B12
.word 0x31632040
.word 0x08AF6899
.word 0x33AC0343
.word 0x650857C0
.word 0x431D0A28
.word 0x463318EE
.word 0x23C955AE
.word 0x04B6107A
.word 0x067D389A
.word 0x692F67C3
.word 0x79AD342F
.word 0x75233411
.word 0x7D1F406C
.word 0x6C862F2A
.word 0x24595C08
.word 0x6C0A5DB4
.word 0x73CC202E
.word 0x18283F4E
.word 0x64BD53F9
.word 0x30EF646C
.word 0x3BF73BAE
.word 0x168F05F6
.word 0x1F321FBB
.word 0x0AA47AA0
.word 0x15414773
.word 0x3A442608
.word 0x5CFF6387
.word 0x5CC73D91
.word 0x46F82444
.word 0x73597F01
.word 0x7DD6778E
.word 0x754134DD
.word 0x69922AA0
.word 0x74EE2480
.word 0x19566B81
.word 0x09C641FD
.word 0x60346645
.word 0x0AAE45BA
.word 0x10897A09
.word 0x65597FC9
.word 0x022F41AC
.word 0x1E520505
.word 0x4F666C4D
.word 0x45C711F1
.word 0x74802189
.word 0x6D1B3F50
.word 0x3E4E6D71
.word 0x692A6484
.word 0x334D704E
.word 0x6D5943A7
.word 0x63904E14
.word 0x4B655B6B
.word 0x4B6D19A6
.word 0x63E97AB2
.word 0x34E737CF
.word 0x13AC71EC
.word 0x43DF75FC
.word 0x29B17E34
.word 0x18F950BB
.word 0x31FC4A2A
.word 0x374F25F4
.word 0x2124208E
.word 0x18D84EE9
.word 0x2C9D2CA1
.word 0x1D975DEF
.word 0x5BC2643C
.word 0x41837BEA
.word 0x1DA577AD
.word 0x4539218A
.word 0x6F976355
.word 0x35642847
.word 0x60767F02
.word 0x7CE86F1D
.word 0x7CB9270D
.word 0x6DD10F07
.word 0x6F3C5B33
.word 0x6CFF5B3E
.word 0x62CC6F34
.word 0x2C8D292E
.word 0x7072292D
.word 0x21061C3D
.word 0x268069B6
.word 0x1D47713B
.word 0x745D39BB
.word 0x413205A7
.word 0x070F5A1B
.word 0x271716A7
.word 0x628D3102
.word 0x7BE373C5
.word 0x43C23107
.word 0x6E06216B
.word 0x17611605
.word 0x1F26271D
.word 0x116C13B9
.word 0x04850578
.word 0x31825220
.word 0x62320FEE
.word 0x3FEB538E
.word 0x4CF3263F
.word 0x0F64208E
.word 0x5EEE09B6
.word 0x0FAC557D
.word 0x0B194A29
.word 0x7CCB6DE5
.word 0x3B6706AE
.word 0x3725699A
.word 0x25B07E1D
.word 0x10422797
.word 0x035C2B4A
.word 0x185A1296
.word 0x17D768FF
.word 0x38A37B71
.word 0x31B559BC
.word 0x265B3D3B
.word 0x12A00F2D
.word 0x7A94071D
.word 0x6A052D6F
.word 0x7AC367F2
.word 0x4E820603
.word 0x5E0777A2
.word 0x620E668E
.word 0x1B393A3F
.word 0x0CE61756
.word 0x0BB718E1
.word 0x7B3B457D
.word 0x6EF00C42
.word 0x499D54FB
.word 0x1AAF5518
.word 0x0C25565D
.word 0x64295E36
.word 0x1C651C3F
.word 0x0DC52461
.word 0x5A102C8A
.word 0x45AD3FF3
.word 0x4A6A096E
.word 0x01196C32
.word 0x426E0E1E
.word 0x4056286D
.word 0x07C15B4F
.word 0x07984EDC
.word 0x14590F6E
.word 0x18853D35
.word 0x68EC46A4
.word 0x387D6B0E
.word 0x1A1B1E8A
.word 0x0FAB09F6
.word 0x045B39AC
.word 0x6CCD0B51
.word 0x52A77EBF
.word 0x79C327F7
.word 0x43E80FA2
.word 0x2CD9458C
.word 0x5B1F3417
.word 0x02D4559D
.word 0x6658343E
.word 0x4DBE0A7F
.word 0x084F5ED5
.word 0x24717DE8
.word 0x30DF3731
.word 0x3EE6254A
.word 0x302E06FB
.word 0x4B3B2FF3
.word 0x509A4FAC
.word 0x07862AE6
.word 0x236257C6
.word 0x2C5C0676
.word 0x6C154FD8
.word 0x741F59A8
.word 0x56BB4B2F
.word 0x4B0B7F46
.word 0x64C4085C
.word 0x740068C3
.word 0x3CB4456A
.word 0x2E0D42D2
.word 0x488C1BDC
.word 0x26C047C5
.word 0x4EF72068
.word 0x45305BA6
.word 0x733A4276
.word 0x19C64E17
.word 0x47D82757
.word 0x7ED05DE9
.word 0x60087D46
.word 0x35C45A7F
.word 0x0BD8021F
.word 0x0D547EE1
.word 0x2B1D39E1
.word 0x5C35629F
.word 0x432210E5
.word 0x5CAF1C6C
.word 0x430C65DB
.word 0x34E57276
.word 0x230E378A
.word 0x37E23486
.word 0x4A527244
.word 0x2B671BDC
.word 0x67A2192A
.word 0x1E774CC8
.word 0x28DA4725
.word 0x1C9F5608
.word 0x7D0E439F
.word 0x4A0549E5
.word 0x4D7B2705
.word 0x34374D0C
.word 0x592E4AFE
.word 0x63B1372D
.word 0x1F760268
.word 0x7A2C2155
.word 0x050B5517
.word 0x69A97E0C
.word 0x1FFB3B4C
.word 0x1041172E
.word 0x565814F7
.word 0x44A90D8A
.word 0x3BA358AC
.word 0x1F87363C
.word 0x58F73667
.word 0x0D7871CA
.word 0x4BF52A00
.word 0x75DE5901
.word 0x6873396C
.word 0x026A5B8D
.word 0x48E45AB9
.word 0x536D2C5B
.word 0x79853DC8
.word 0x2CDE17AF
.word 0x2A4D75C7
.word 0x682A1F04
.word 0x13923E75
.word 0x36BF76A7
.word 0x797B5915
.word 0x01574112
.word 0x7A293D2F
.word 0x70042409
.word 0x12A4190A
.word 0x67001376
.word 0x06875DE9
.word 0x04326E05
.word 0x166B5408
.word 0x6980477F
.word 0x31157254
.word 0x5FD77CE8
.word 0x0B5F75EE
.word 0x1EFB6E57
.word 0x4AE7755E
.word 0x46107A98
.word 0x2F796B97
.word 0x50E41883
.word 0x673D76AF
.word 0x16022A1A
.word 0x79A0465B
.word 0x19776564
.word 0x7503762C
.word 0x40626F0D
.word 0x4B264F8B
.word 0x313D02BA
.word 0x08532F75
.word 0x6CEE452E
.word 0x514A0BF7
.word 0x6C8D1C1E
.word 0x53F05569
.word 0x4FF327D4
.word 0x16B62F6A
.word 0x69073A86
.word 0x52CA3D9F
.word 0x2FC86973
.word 0x4500002A
.word 0x6B1A13C3
.word 0x217F7BEC
.word 0x1A507B1C
.word 0x162B2A7B
.word 0x6B7D4A04
.word 0x07D66DE2
.word 0x4A7A23F9
.word 0x7626041B
.word 0x54B71B52
.word 0x3244364D
.word 0x3DC328D4
.word 0x54493FC6
.word 0x70990113
.word 0x1B6928B6
.word 0x79B0638F
.word 0x24DD10B1
.word 0x05C13F8A
.word 0x259224E3
.word 0x01564AAA
.word 0x12933E10
.word 0x25176553
.word 0x64376253
.word 0x7AD468C2
.word 0x600A2692
.word 0x27513AEA
.word 0x157C2BC4
.word 0x04D5440F
.word 0x794C33E2
.word 0x5A712223
.word 0x4BB20AAE
.word 0x3C1135E3
.word 0x354F3E27
.word 0x5F4465B1
.word 0x46D562C7
.word 0x70CB3230
.word 0x47765F82
.word 0x36E378A1
.word 0x7E0E7D7F
.word 0x0C527F01
.word 0x610F3794
.word 0x003325DE
.word 0x59300584
.word 0x26825BFD
.word 0x02D51EF8
.word 0x65672FAD
.word 0x1A3D723E
.word 0x4B4319E9
.word 0x7E6D4AC3
.word 0x397B5F31
.word 0x76E06351
.word 0x70072225
.word 0x27EB6009
.word 0x45B903E6
.word 0x61F26C20
.word 0x194E6E2C
.word 0x374D7759
.word 0x47366327
.word 0x04F84F46
.word 0x30236F17
.word 0x59FC103E
.word 0x1C5317AA
.word 0x69A12A1D
.word 0x079E6519
.word 0x745074BF
.word 0x223F6101
.word 0x534A103A
.word 0x12622702
.word 0x130B0CDD
.word 0x42716319
.word 0x487C16EC
.word 0x481F59BE
.word 0x0CDB2219
.word 0x303155BD
.word 0x4C6B50C3
.word 0x3B0F17D4
.word 0x53DB12EE
.word 0x560E2411
.word 0x48773905
.word 0x5D7A08EA
.word 0x77107651
.word 0x73677C19
.word 0x25AC0F38
.word 0x7735693E
.word 0x53EE2F36
.word 0x69E44E32
.word 0x1644229D
.word 0x4B1D012C
.word 0x77D2700C
.word 0x3AFB3C96
.word 0x0F220DB1
.word 0x6C9E0CAD
.word 0x31882E3E
.word 0x356F7ADB
.word 0x715661AC
.word 0x453012D4
.word 0x52C505B2
.word 0x52CA1D72
.word 0x639E4204
.word 0x49D62D51
.word 0x21AB0C4C
.word 0x44E9592A
.word 0x5BE16FE9
.word 0x60A03FF0
.word 0x7A4A156A
.word 0x336F32AD
.word 0x58B445C9
.word 0x76282019
.word 0x201C6567
.word 0x294D1DFF
.word 0x4AD822CB
.word 0x43172C50
.word 0x3F86551B
.word 0x32430E04
.word 0x2EB74656
.word 0x419F53B4
.word 0x1F5B6557
.word 0x285873F9
.word 0x55EC1B8A
.word 0x53000D82
.word 0x025B426B
.word 0x31622EF7
.word 0x60BB74C3
.word 0x15064091
.word 0x38AE37A2
.word 0x6C826B76
.word 0x6792371B
.word 0x67871AD5
.word 0x616C12C2
.word 0x4FA772C6
.word 0x549175E6
.word 0x21E758DF
.word 0x5C16778F
.word 0x35096A95
.word 0x6CFD7E36
.word 0x78967D59
.word 0x6A1C2347
.word 0x18AD046E
.word 0x0ACC5257
.word 0x128E788C
.word 0x00572025
.word 0x05E61D37
.word 0x061F1552
.word 0x4ED83FDC
.word 0x488E68E0
.word 0x34CF4CB0
.word 0x4EC1666C
.word 0x3A065549
.word 0x52F47C2B
.word 0x57D464F9
.word 0x35AC2CA6
.word 0x33B93EED
.word 0x77A66035
.word 0x1929620A
.word 0x6682523D
.word 0x441A6E83
.word 0x682F1629
.word 0x484F493A
.word 0x11157029
.word 0x216218DC
.word 0x71067DAD
.word 0x379478BB
.word 0x42E269A0
.word 0x65557D6A
.word 0x6B0C2865
.word 0x4992671A
.word 0x70907792
.word 0x72C11DB7
.word 0x5D101D6F
.word 0x2EAD52C2
.word 0x2F73242D
.word 0x0B0164ED
.word 0x4D4D0CE6
.word 0x52976178
.word 0x1F0D3658
.word 0x137E3F4E
.word 0x42E97361
.word 0x79CD2FDE
.word 0x028A0D3A
.word 0x0B2A21BA
.word 0x77772D73
.word 0x0F1950F2
.word 0x0A426BB2
.word 0x3006012F
.word 0x38747B2B
.word 0x21113D8E
.word 0x4D3933DF
.word 0x549B3A42
.word 0x78CB7394
.word 0x0F9433E8
.word 0x729F1297
.word 0x658368A9
.word 0x12526834
.word 0x69520712
.word 0x0B521AF2
.word 0x1EDF2EB3
.word 0x374C388F
.word 0x79435E79
.word 0x1B5951BE
.word 0x71E06CCB
.word 0x13E815A3
.word 0x042D6567
.word 0x5369290A
.word 0x1A4168FB
.word 0x1FBF356B
.word 0x36206A83
.word 0x7A636B9E
.word 0x63C96665
.word 0x1F57765E
.word 0x3FFB6F4E
.word 0x06D1187F
.word 0x1FCB2CCA
.word 0x55A472EF
.word 0x24E727A6
.word 0x686E2E6E
.word 0x4AA70006
.word 0x6584050D
.word 0x37D96945
.word 0x019E6768
.word 0x6149078F
.word 0x634139A3
.word 0x49120B40
.word 0x50F06425
.word 0x66A825FB
.word 0x16113417
.word 0x03A1358A
.word 0x4AA1479B
.word 0x19464079
.word 0x699701CD
.word 0x7ADD2071
.word 0x6219427A
.word 0x58B47655
.word 0x0F625DA2
.word 0x67EE441E
.word 0x436E0EB0
.word 0x3B0D4877
.word 0x506A6374
.word 0x17437818
.word 0x3CDE5AE4
.word 0x527830E3
.word 0x0E983397
.word 0x061A02BF
.word 0x585825FD
.word 0x22A92A38
.word 0x763D065F
.word 0x2FFE18D3
.word 0x24F20A9A
.word 0x465E2732
.word 0x5F982F9B
.word 0x0C424CEC
.word 0x30727A99
.word 0x44E47A2A
.word 0x60521215
.word 0x3B896F02
.word 0x30C76A93
.word 0x17912C93
.word 0x0D030315
.word 0x65405BE5
.word 0x5D8E6D5C
.word 0x5F4A467E
.word 0x6AAD1DDE
.word 0x45203CC3
.word 0x79903F86
.word 0x49FD0615
.word 0x103E072E
.word 0x68AF36A7
.word 0x0C4142DD
.word 0x28260721
.word 0x781120C0
.word 0x1CBE09F6
.word 0x4B4169EA
.word 0x324C5A86
.word 0x016B2CCB
.word 0x0AEA21F3
.word 0x33DD1372
.word 0x7E830DC3
.word 0x22006182
.word 0x071D143A
.word 0x548C55F6
.word 0x25E92275
.word 0x476E6C94
.word 0x0D0C1046
.word 0x46743B32
.word 0x1A2B75D3
.word 0x68BE66AC
.word 0x6DB93EED
.word 0x56E56BA0
.word 0x2B001831
.word 0x47E836F0
.word 0x2CF011E1
.word 0x60DB49F5
.word 0x3BAB1480
.word 0x634E6683
.word 0x0ECC032F
.word 0x567E7EA1
.word 0x287B27CA
/****************************************************************
DMA TEST #4.65
****************************************************************/
ori $1, $0, 0x0041 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0x0B00 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
Prep65: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep65 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write65 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x173E /* load random number */
ori $9, $9, 0x6405
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read65 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk65: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk65 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln65 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.66
****************************************************************/
ori $1, $0, 0x0042 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0010 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2810
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
Prep66: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep66 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write66 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x5532 /* load random number */
ori $9, $9, 0x44C2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read66 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk66: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk66 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln66 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.67
****************************************************************/
ori $1, $0, 0x0043 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
Prep67: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep67 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write67 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7AA3 /* load random number */
ori $9, $9, 0x7352
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read67 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk67: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk67 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln67 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.68
****************************************************************/
ori $1, $0, 0x0044 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
Prep68: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep68 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write68 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x5C4C /* load random number */
ori $9, $9, 0x68B8
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read68 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk68: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk68 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln68 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.69
****************************************************************/
ori $1, $0, 0x0045 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0x0C00 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
Prep69: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep69 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write69 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x6F72 /* load random number */
ori $9, $9, 0x3710
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read69 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk69: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk69 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln69 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.70
****************************************************************/
ori $1, $0, 0x0046 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
Prep70: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep70 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write70 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x2D52 /* load random number */
ori $9, $9, 0x5FDE
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read70 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk70: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk70 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln70 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.71
****************************************************************/
ori $1, $0, 0x0047 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
Prep71: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep71 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write71 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4A4A /* load random number */
ori $9, $9, 0x3E6F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read71 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk71: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk71 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln71 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.72
****************************************************************/
ori $1, $0, 0x0048 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
Prep72: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep72 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write72 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1605 /* load random number */
ori $9, $9, 0x5F0E
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read72 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk72: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk72 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln72 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.73
****************************************************************/
ori $1, $0, 0x0049 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0807
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0808 /* len of data (bytes) */
Prep73: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep73 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write73 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x2892 /* load random number */
ori $9, $9, 0x23BB
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read73 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0808 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk73: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk73 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln73 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.74
****************************************************************/
ori $1, $0, 0x004A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0807
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0808 /* len of data (bytes) */
Prep74: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep74 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write74 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4D2B /* load random number */
ori $9, $9, 0x44A8
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read74 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0808 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk74: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk74 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln74 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.75
****************************************************************/
ori $1, $0, 0x004B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0807
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0808 /* len of data (bytes) */
Prep75: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep75 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write75 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1620 /* load random number */
ori $9, $9, 0x7E9E
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read75 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0808 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk75: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk75 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln75 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.76
****************************************************************/
ori $1, $0, 0x004C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x080F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0810 /* len of data (bytes) */
Prep76: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep76 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write76 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x5E1A /* load random number */
ori $9, $9, 0x0B2C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x080C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read76 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0810 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk76: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk76 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln76 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.77
****************************************************************/
ori $1, $0, 0x004D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0FF7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
Prep77: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep77 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write77 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x61AE /* load random number */
ori $9, $9, 0x3E19
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FF4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read77 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0FF8 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk77: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk77 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln77 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.78
****************************************************************/
ori $1, $0, 0x004E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0FF7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
Prep78: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep78 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write78 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4105 /* load random number */
ori $9, $9, 0x499B
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FF4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read78 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0FF8 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk78: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk78 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln78 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #4.79
****************************************************************/
ori $1, $0, 0x004F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0FFF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x1000 /* len of data (bytes) */
Prep79: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep79 /* done? */
nop /* bne delay slot */
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write79 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4BFD /* load random number */
ori $9, $9, 0x2641
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FFC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read79 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x1000 /* len of data (bytes) */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk79: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk79 /* check if done */
nop /* bne delay slot */
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln79 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break