/************************************************************************
  WHAT: RSP SCALAR UNIT DMA VERIFICATION TEST GENERATOR
  SCCS: %W% %G%
  PTLS: $Id: dmagen.h,v 1.1.1.1 2002/05/02 03:29:13 blythe Exp $
  FILE: dmagen.h
  ENGR: Evan Y. Wang
  PROJ: Project Reality
  (CR): 1994 Silicon Graphics, Inc.
 ************************************************************************/
#ifndef _dmagen_h_
#define _dmagen_h_

#define IMEM_BASE	0x04001000
#define DMEM_BASE	0x04000000
#define DMEM_SIZE	0x1000		/* 4KB (in # bytes)		*/
#define PAGE_SIZE	0x1000
/************************************************************************
  32KB fake RDRAM (in # bytes)

  0x0000 - 0x5FFF	sequential value
  0x6000 - 0x6FFF	JR $31		<= used in IMEM test
  0x7000 - 0x7FFF	ADDI's		<= used in IMEM test
 ************************************************************************/
#define DRAM_SIZE	0x7000
#define DRAM_JRSEG	5
#define DRAM_ADDISEG	6

/************************************************************************
  CPU0 REGISTER LAYOUT

  0: DMA_SP_ADDRESS - 13 bit IMEM/DMEM start address to DMA data to/from DRAM.

	[12]	- 0 = DMEM, 1 = IMEM
	[11:0]	- DMEM/IMEM byte address

  1: DMA_DBUS_ADDRESS - 24 bit DRAM start address to DMA data to/from DMEM.

  2: DMA_READ_LENGTH - skip, count, length for DRAM to DMEM DMA.

	[31:20]	- number of bytes to skip between each span
	[19:12]	- number of spans - 1 (i.e. 0 means copy 1 span)
	[11:0]	- number of bytes to copy - 1 (i.e 0 means copy 1 byte)

  3: DMA_WRITE_LENGTH - skip, count, length for DMEM to DRAM DMA.

	[31:20]	- number of bytes to skip between each span
	[19:12]	- number of spans - 1 (i.e. 0 means copy 1 span)
	[11:0]	- number of bytes to copy - 1 (i.e 0 means copy 1 byte)

  4: SP status/control.

	[3]	- broke
	[2]	- halt
	[1]	- full
	[0]	- busy

  5: DMA_FULL
  6: DMA_BUSY
  7: Reserved
  8: DMA_START_ADDRESS - 24 bit DRAM address to DMA data to the DP command FIFO.
  9: DMA_END_ADDRESS - 24 bit DRAM address to DMA data to the DP command FIFO.
 10: DMA_CURRENT_ADDRESS - 24 bit DRAM address to DMA data to the DP
     command FIFO (read only).
 11: DP status/control (TBD).
 12: COUNTER_CLOCK - 24 bits, free running counter
 13: COUNTER_CBUF_CMD - 24 bits, number of clocks the DP command buffer is
     not empty.
 14: COUNTER_CBUF_PIPE - 24 bits, number of clocks the DP pipeline is
     not stalled.
 15: COUNTER_TMEM - 24 bits, number of clocks spent loading TMEM.
 Note: The bottom three bits of all address and byte length registers are
       ignored.
 ************************************************************************/
typedef struct {

    u32 flag;

    union {
	struct {
	    u32     :19;
	    u32 sel : 1;
	    u32	adr :12;
	} u;
	u32 w;
    } mem;

    union {
	struct {
	    u32     : 8;
	    u32 adr :24;
	} u;
	u32 w;
    } ram;

    union {
	struct {
	    u32 skp :12;
	    u32 spn : 8;
	    u32 len :12;
	} u;
	u32 w;
    } len;

} DMA;

/************************************************************************
  REGISTER DEFINITIONS
 ************************************************************************/
#define R0		0
#define R1		1
#define R2		2
#define R3		3
#define R4		4
#define R5		5
#define R6		6
#define R7		7
#define R8		8
#define R9		9
#define R10		10
#define R11		11
#define R12		12
#define R13		13
#define R14		14
#define R15		15
#define R16		16
#define R17		17
#define R18		18
#define R19		19
#define R20		20
#define R21		21
#define R22		22
#define R23		23
#define R24		24
#define R25		25
#define R26		26
#define R27		27
#define R28		28
#define R29		29
#define R30		30
#define R31		31

#define CP0_0		0
#define CP0_1		1
#define CP0_2		2
#define CP0_3		3
#define CP0_4		4
#define CP0_5		5
#define CP0_6		6
#define CP0_7		7
#define CP0_8		8
#define CP0_9		9
#define CP0_10		10
#define CP0_11		11
#define CP0_12		12
#define CP0_13		13
#define CP0_14		14
#define CP0_15		15

#define CP0_DMEM	CP0_0
#define CP0_IMEM	CP0_0
#define IMEM_FLAG	0x100
#define CP0_DRAM	CP0_1
#define CP0_RLEN	CP0_2
#define CP0_WLEN	CP0_3
#define CP0_STAT	CP0_4
#define CP0_FULL	CP0_5
#define CP0_BUSY	CP0_6
#define CP0_SGNL	CP0_7
#define STAT_HALT_BIT	0x1
#define STAT_BROK_BIT	0x2
#define STAT_BUSY_BIT	0x4
#define STAT_FULL_BIT	0x8

#define JR_R31		0x03E00008	/* a special jump instr in bin	*/

#define Comment(s)	fprintf(fhTFile,"\t%s\n",s)
#define Newline()	fprintf(fhTFile,"\n")

/************************************************************************
  GLOBAL VARIABLES
 ************************************************************************/
extern	u32	Ip;
extern	u32	Reg[];
extern	FILE	*fhTFile;

extern	void	Label();
extern  void	LdReg();
extern  void	TestHeader();

extern	void	Addi();
extern	void	Andi();
extern	void	Beq();
extern	void	Bne();
extern	void	Break();
extern	void	J();
extern	void	Jal();
extern	void	Jalr();
extern	void	Jr();
extern	void	Lli();
extern	void	Lw();
extern	void	Mfc0();
extern  void	Mtc0();
extern	void	Nop();
extern	void	Ori();
extern	void	Sll();
extern	void	Srl();
extern	void	Sub();

#endif