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/************************************************************************
DMA READ TESTS: File #0
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/****************************************************************
DMA TEST #0.1
****************************************************************/
ori $1, $0, 0x0001 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x0080 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read1: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read1 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk1: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk1 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x4232 /* load random number */
ori $9, $9, 0x5770
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.2
****************************************************************/
ori $1, $0, 0x0002 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read2: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read2 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk2: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk2 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x30E1 /* load random number */
ori $9, $9, 0x19A5
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.3
****************************************************************/
ori $1, $0, 0x0003 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0100 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read3: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read3 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk3: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk3 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x5025 /* load random number */
ori $9, $9, 0x008C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.4
****************************************************************/
ori $1, $0, 0x0004 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0200 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read4: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read4 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk4: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk4 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x352C /* load random number */
ori $9, $9, 0x77A1
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.5
****************************************************************/
ori $1, $0, 0x0005 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0x0400 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read5: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read5 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk5: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk5 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x25F4 /* load random number */
ori $9, $9, 0x5E9F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.6
****************************************************************/
ori $1, $0, 0x0006 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0x0800 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read6: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read6 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk6: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk6 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x2D08 /* load random number */
ori $9, $9, 0x3D29
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.7
****************************************************************/
ori $1, $0, 0x0007 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FF0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $12, 0x1000 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read7: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read7 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk7: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk7 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x10B8 /* load random number */
ori $9, $9, 0x4BD4
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.8
****************************************************************/
ori $1, $0, 0x0008 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FF8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3008
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read8: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read8 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk8: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk8 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x15C5 /* load random number */
ori $9, $9, 0x272C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0004 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.9
****************************************************************/
ori $1, $0, 0x0009 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x2000 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read9: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read9 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk9: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk9 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6234 /* load random number */
ori $9, $9, 0x4EFF
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.10
****************************************************************/
ori $1, $0, 0x000A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x4000 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read10: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read10 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk10: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk10 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6FC7 /* load random number */
ori $9, $9, 0x7817
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.11
****************************************************************/
ori $1, $0, 0x000B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x8000 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read11: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read11 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk11: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk11 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7656 /* load random number */
ori $9, $9, 0x2031
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.12
****************************************************************/
ori $1, $0, 0x000C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0xC000 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read12: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read12 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk12: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk12 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x3CEF /* load random number */
ori $9, $9, 0x33CB
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.13
****************************************************************/
ori $1, $0, 0x000D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0xA000 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read13: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read13 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk13: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk13 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x058C /* load random number */
ori $9, $9, 0x5B1D
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.14
****************************************************************/
ori $1, $0, 0x000E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FE8
lui $12, 0x0180 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read14: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read14 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk14: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk14 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x79C8 /* load random number */
ori $9, $9, 0x1F60
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.15
****************************************************************/
ori $1, $0, 0x000F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0x0280 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read15: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read15 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk15: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk15 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x4FCD /* load random number */
ori $9, $9, 0x7B2E
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.16
****************************************************************/
ori $1, $0, 0x0010 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FE8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read16: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read16 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk16: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk16 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7D76 /* load random number */
ori $9, $9, 0x009C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.17
****************************************************************/
ori $1, $0, 0x0011 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FF0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read17: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read17 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk17: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk17 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6C62 /* load random number */
ori $9, $9, 0x7D64
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.18
****************************************************************/
ori $1, $0, 0x0012 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E0
lui $12, 0x0480 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read18: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read18 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk18: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk18 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6C5F /* load random number */
ori $9, $9, 0x5931
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.19
****************************************************************/
ori $1, $0, 0x0013 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x0880 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read19: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read19 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk19: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk19 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x4A78 /* load random number */
ori $9, $9, 0x43F2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.20
****************************************************************/
ori $1, $0, 0x0014 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x1080 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read20: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read20 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk20: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk20 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x2996 /* load random number */
ori $9, $9, 0x19BA
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.21
****************************************************************/
ori $1, $0, 0x0015 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x2080 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read21: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read21 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk21: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk21 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x2E67 /* load random number */
ori $9, $9, 0x1799
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.22
****************************************************************/
ori $1, $0, 0x0016 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x4080 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read22: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read22 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk22: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk22 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x730C /* load random number */
ori $9, $9, 0x0874
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.23
****************************************************************/
ori $1, $0, 0x0017 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x8080 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read23: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read23 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk23: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk23 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x37C0 /* load random number */
ori $9, $9, 0x62C2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.24
****************************************************************/
ori $1, $0, 0x0018 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FE8
lui $12, 0x0300 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read24: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read24 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk24: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk24 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1475 /* load random number */
ori $9, $9, 0x57BC
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.25
****************************************************************/
ori $1, $0, 0x0019 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0x0500 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read25: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read25 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk25: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk25 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x3C19 /* load random number */
ori $9, $9, 0x025E
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.26
****************************************************************/
ori $1, $0, 0x001A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FE0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read26: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read26 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk26: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk26 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x5CFB /* load random number */
ori $9, $9, 0x284C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.27
****************************************************************/
ori $1, $0, 0x001B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FE8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read27: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read27 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk27: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk27 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x0297 /* load random number */
ori $9, $9, 0x487E
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.28
****************************************************************/
ori $1, $0, 0x001C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $12, 0x0900 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read28: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read28 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk28: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk28 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x43A6 /* load random number */
ori $9, $9, 0x7335
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.29
****************************************************************/
ori $1, $0, 0x001D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2788
lui $12, 0x1100 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read29: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read29 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk29: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk29 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x2C40 /* load random number */
ori $9, $9, 0x0CB1
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.30
****************************************************************/
ori $1, $0, 0x001E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2790
lui $12, 0x2100 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read30: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read30 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk30: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk30 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6686 /* load random number */
ori $9, $9, 0x179C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.31
****************************************************************/
ori $1, $0, 0x001F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0788 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x4100 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read31: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read31 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk31: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk31 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x54FE /* load random number */
ori $9, $9, 0x6621
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.32
****************************************************************/
ori $1, $0, 0x0020 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0790 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x8100 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read32: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read32 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk32: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk32 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x50A5 /* load random number */
ori $9, $9, 0x0834
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.33
****************************************************************/
ori $1, $0, 0x0021 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x0600 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read33: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read33 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk33: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk33 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x3972 /* load random number */
ori $9, $9, 0x6B6C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.34
****************************************************************/
ori $1, $0, 0x0022 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0A00 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read34: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read34 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk34: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk34 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x32B0 /* load random number */
ori $9, $9, 0x547F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #0.35
****************************************************************/
ori $1, $0, 0x0023 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x1200 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read35: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read35 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk35: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk35 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6D7E /* load random number */
ori $9, $9, 0x1443
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break