/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

/*
 * File:	rspctl.c
 * Creator:	hsa@sgi.com
 * Create Date:	Tue Feb  8 11:50:41 PST 1994
 *
 * This file is the control unit for the RSP simulator.
 *
 */

#include <stdio.h>
#include "rsp.h"
#include "rspctl.h"
#include "memory.h"
#include "cop0.h"
#include "opcode.h"
#include "su.h"
#include "vu.h"
#include "std_cmds.h"


/*
 * The RSP clock.
 */
u32	rsp_clock;

/*
 * The RSP PC, points into the instruction cache.
 */
u32	rsp_programCounter;

/*
 * Temp PC, set during execution cycle, updates the real PC
 * at the end of the instruction.
 *
 * After the execution cycle, if the clock is equal to the
 * value of delayClock, the PC is modified.
 */
static u32	tempPC;
static u32	delayClock;
#define rsp_DELAY_INVALID	0xffffffff

static boolean	rsp_LoadStoreSlip[2];

/*
 * The RSP control register, accessible to the host processor.
 */
u32	rsp_controlReg;

typedef struct {
    int		count;
    int		waiting;
} rsp_SUStall_t;

rsp_SUStall_t	rsp_SURegStalls[32];

/*
 * RSP step functions, implemented in each module, they execute one clock
 * step. Each module installs these during their own init.
 */
rsp_stepProc_t	rsp_procStepProcs[rsp_STEP_PROC_MAX];
static int	rsp_stepProcCount = 0;

/*
 * Breakpoints. List of addresses or clock values.
 */
typedef struct {
    u32		where;
    boolean	isAddr;
    boolean	enabled;
    int		cmdCnt;
    char	*cmd[16];
} rsp_bkpt_t;
#define rsp_BREAK_COUNT_MAX	32
static rsp_bkpt_t	rsp_breakPoints[rsp_BREAK_COUNT_MAX];
static int		rsp_breakCount = 0;

static u32		rsp_watchPoints[rsp_BREAK_COUNT_MAX];
static int		rsp_watchCount = 0;

/*
 * fetched and execute instructions:
 */
typedef struct {
    i16		group_size;
    u32		instV, instS;
    u32		pcV, pcS;
    boolean	validV, validS;
    boolean	Vfirst;
    boolean	SisLoad;
    boolean	SisStore;
} rsp_instGroup_t;

static rsp_instGroup_t	rsp_fetchInst, rsp_execInst;

/*
 * Per-clock tick function.
 */
static boolean	rsp_InstFetch(void);
static boolean	rsp_InstExec(void);
static boolean	rsp_SUStaller(void);
static boolean	rsp_SUAddLocks(u32 inst);
static boolean	rsp_SUCheckLocks(u32 inst);

static boolean	inst_is_scalar(u32 inst);

/*
 * reset processor state.
 */
/* passing pc argument during initialization (Kishor 9/26/94)*/
void
rsp_ProcessorReset(int pc)
{
    rsp_clock = 0;
    rsp_programCounter = pc;
    rsp_controlReg = 0x0;
    tempPC = 0;
    delayClock = rsp_DELAY_INVALID;

    bzero((char *)&rsp_fetchInst, sizeof(rsp_instGroup_t));
    bzero((char *)&rsp_execInst, sizeof(rsp_instGroup_t));

    /* clear registers... */
}

/*
 * RSP control logic initialize.
 */
void
rsp_ProcessorInit(void)
{
    rsp_ProcessorReset(rsp_ICACHE_LOW);
    rsp_controlReg = Flag(rsp_controlReg, rsp_CtlHaltMask);

    /* clear out step proc list */
    bzero((void *) &(rsp_procStepProcs[0]), 
	  (rsp_STEP_PROC_MAX * sizeof(rsp_stepProc_t)));
    rsp_stepProcCount = 0;

    rsp_LoadStoreSlip[0] = FALSE;
    rsp_LoadStoreSlip[1] = FALSE;

    /*
     * control step installs:
     * Exec is before fetch so we exec previously fetched instruction.
     */
    rsp_ProcessorStepInstall(rsp_SUStaller);
    rsp_ProcessorStepInstall(rsp_InstExec);
    rsp_ProcessorStepInstall(rsp_InstFetch);
}

/*
 * This function is called form other modules, it installs
 * a 'step' routine, that will be executed once per clock tick.
 */
void
rsp_ProcessorStepInstall(rsp_stepProc_t StepProc)
{
    rsp_procStepProcs[rsp_stepProcCount++] = StepProc;
}

/*
 * This function is called to install a breakpoint at the
 * specified address.
 */
void
rsp_ProcessorBreakpointInstall(u32 where, boolean isAddr)
{
    if (rsp_breakCount < rsp_BREAK_COUNT_MAX) {
	rsp_breakPoints[rsp_breakCount].where = where;
	rsp_breakPoints[rsp_breakCount].isAddr = isAddr;
	rsp_breakPoints[rsp_breakCount].enabled = TRUE;
	rsp_breakPoints[rsp_breakCount].cmdCnt = 0;
	rsp_breakCount++;
    } else {
	/* print error message... */
    }
}

/*
 * init breakpoint commands
 */
void
rsp_ProcessorBreakpointCmdInit(int bp)
{
    register rsp_bkpt_t	*bpp = &(rsp_breakPoints[bp]);
    int		j;

    if (bp < rsp_breakCount) {
	for (j=0; j<bpp->cmdCnt; j++) {
	    if (bpp->cmd[j] != NULL)
		free(bpp->cmd[j]);
	}
	bpp->cmdCnt = 0;
    } else {
	/* print error message... */
    }
}

/*
 * install a command at a breakpoint.
 */
void
rsp_ProcessorBreakpointCmdInstall(int bp, char *string)
{
    register rsp_bkpt_t	*bpp = &(rsp_breakPoints[bp]);

    if (bp < rsp_breakCount) {
	bpp->cmd[bpp->cmdCnt] = (char *) malloc(strlen(string)+1);
	strcpy(bpp->cmd[bpp->cmdCnt++], string);
    } else {
	/* print error message... */
    }
}

/*
 * enable (or disable) a breakpoint.
 */
void
rsp_ProcessorBreakpointEnable(int bp, boolean doEnable)
{
    register rsp_bkpt_t	*bpp = &(rsp_breakPoints[bp]);

    if (bp < rsp_breakCount) {
	bpp->enabled = doEnable;
    } else {
	/* print error message... */
    }
}

/*
 * list out all the breakpoints.
 */
void
rsp_ProcessorBreakpointList(FILE *out)
{
    register rsp_bkpt_t	*bp = &(rsp_breakPoints[0]);
    int			i, j;
    u32			inst;
    char 		instd[32];

    if (rsp_breakCount > 0) {
	rsp_fprintf(out,"\n");
    }

    for (i=0; i<rsp_breakCount; i++, bp++) {
	if (bp->enabled)
	    rsp_fprintf(out," ");
	else
	    rsp_fprintf(out,"d");
	rsp_fprintf(out," [%d]  %08x ", i, bp->where);
	if (bp->isAddr) {
	    inst = rsp_ExamineMemory(bp->where);
	    rsp_DisasmInst(inst, instd, bp->where);
	    rsp_fprintf(out,"\t%s\n",instd);
	} else {
	    rsp_fprintf(out,"(pc)\n");
	}

	for (j=0; j<bp->cmdCnt; j++) {
	    rsp_fprintf(out,"\t%s",bp->cmd[j]);
	}
	rsp_fprintf(out,"\n");
    }

    if (rsp_breakCount > 0) {
	rsp_fprintf(out,"\n");
    }

    fflush(out);
}

/*
 * return 0 if not breakpoint, 1 if active, 2 if inactive
 */
int
rsp_ProcessorBreakpointCheck(u32 addr)
{
    register rsp_bkpt_t	*bp = &(rsp_breakPoints[0]);
    int			i;

    for (i=0; i<rsp_breakCount; i++, bp++) {
	if (bp->where == addr) {
	    return bp->enabled ? 1 : 2;
	}
    }

    return 0;
}

/*
 * return breakpoint number from address
 */

int
rsp_ProcessorBreakpointNumber(u32 addr)
{
    register rsp_bkpt_t	*bp = &(rsp_breakPoints[0]);
    int			i;

    for (i=0; i<rsp_breakCount; i++, bp++) {
	if (bp->where == addr) {
	    return i;
	}
    }

    return -1;
}

/*
 * return all breakpoint addresses and enables in two arrays
 */

int
rsp_ProcessorBreakpointGetAll(u32 addrs[], int enabled[])
{
    register rsp_bkpt_t	*bp = &(rsp_breakPoints[0]);
    int			i;

    for (i=0; i<rsp_breakCount; i++, bp++) {
	addrs[i] = bp->where;
	enabled[i] = bp->enabled;
    }

    return rsp_breakCount;
}


/*
 * This function is called to install a memory watchpoint at the
 * specified address.
 */
void
rsp_ProcessorWatchpointInstall(u32 where)
{
    if (rsp_watchCount < rsp_BREAK_COUNT_MAX) {
	rsp_watchPoints[rsp_watchCount++] = where;
    } else {
	/* print error message... */
    }
}

void
rsp_CheckWatchpoint(u32 addr)
{
    int i;

    for (i=0; i<rsp_watchCount; i++) {
	if (addr == rsp_watchPoints[i]) {
	    rsp_controlReg = Flag(rsp_controlReg, rsp_CtlHaltMask);
	    break;
	}
    }
}

static boolean _doingSSTEP;

/* slip processor 1 clock, for taken branch bubble */
boolean
rsp_ProcessorSlip(boolean doClock)
{
    if (doClock)
	rsp_clock++;
    counter_clock++;
}

boolean
rsp_ProcessorSStep(void)
{
    boolean	retval;
    int		i, j;
    u32		inst;
    int		inst_type;

    /* disable future fetching */
    _doingSSTEP = TRUE;

    /*
     * clear fetched instructions.
     */
    bzero((char *)&rsp_fetchInst, sizeof(rsp_instGroup_t));
    bzero((char *)&rsp_execInst, sizeof(rsp_instGroup_t));

    /*
     * fetch 1 instruction using PC.
     */
    inst = rsp_ExamineMemory1(rsp_programCounter, rsp_ICACHE_ACCESS);

    /*
     * classify the instruction:
     */
    inst_type = inst_is_scalar(inst);
    rsp_fetchInst.group_size = 1;
    if (inst_type) {
	rsp_fetchInst.instS = inst;
	rsp_fetchInst.pcS = rsp_programCounter;
	rsp_fetchInst.validS = TRUE;
	rsp_fetchInst.validV = FALSE;
    } else {
	rsp_fetchInst.instV = inst;
	rsp_fetchInst.pcV = rsp_programCounter;
	rsp_fetchInst.validV = TRUE;
	rsp_fetchInst.validS = FALSE;
    }

    /*
     * execute that instruction.
     */
    /* do each thing in the list.. */
    for (i=0; i<rsp_stepProcCount; i++) {
	if (rsp_procStepProcs[i] != (rsp_stepProc_t) NULL) {
	    retval = (*rsp_procStepProcs[i])();
	}
    }
    bzero((char *)&rsp_fetchInst, sizeof(rsp_instGroup_t));

    /*
     * run the clock till it's done.
     */
    for (j=0; j<10; j++) {
	/* do each thing in the list.. */
	for (i=0; i<rsp_stepProcCount; i++) {
	    if (rsp_procStepProcs[i] != (rsp_stepProc_t) NULL) {
		retval = (*rsp_procStepProcs[i])();
	    }
	}
    }

    rsp_clock++;

    /*
     * clear fetched instructions.
     */
    bzero((char *)&rsp_fetchInst, sizeof(rsp_instGroup_t));
    bzero((char *)&rsp_execInst, sizeof(rsp_instGroup_t));

    _doingSSTEP = FALSE;

    return(TRUE);
}

/*
 * Step RSP one clock tick.
 */
boolean
rsp_ProcessorStep(void)
{
    register rsp_bkpt_t	*bp;
    boolean	retval, do_continue = TRUE;
    int		i, j;
    char	cmd[32];

    /* do each thing in the list.. */
    for (i=0; i<rsp_stepProcCount; i++) {
	if (rsp_procStepProcs[i] != (rsp_stepProc_t) NULL) {
	    retval = (*rsp_procStepProcs[i])();
	}
    }

    rsp_clock++;

    /*
     * check for somebody that has halted the processor;
     * could be memory watchpoint, exception, etc.
     */
    if (Flagged(rsp_controlReg, rsp_CtlHaltMask)) {
	do_continue = FALSE;
    }

    /*
     * Check for breakpoint...
     */
    bp = &(rsp_breakPoints[0]);
    for (i=0; i<rsp_breakCount && do_continue; i++, bp++) {
	if (bp->enabled && bp->isAddr) { /* PC */
	    if (rsp_programCounter == bp->where) {
		do_continue = FALSE;
	    }
	} else if (bp->enabled) {		/* clock */
	    if (rsp_clock == bp->where) {
		do_continue = FALSE;
	    }
	}

	if (!do_continue) {
	    rsp_Verbose(stderr,"break: [%d] RSP halted at PC = 0x%08x CLK = 0x%08x\n",
		    i, rsp_programCounter, rsp_clock);
	    for (j=0; j<bp->cmdCnt; j++) {
		sscanf(bp->cmd[j],"%s",cmd);
		process_command(cmd, bp->cmd[j], stdin);
	    }
	}
    }

    return(do_continue);
}

/*
 * Run RSP (until breakpoint or completion)
 */
void
rsp_ProcessorRun(void)
{
    boolean	do_continue = TRUE;
    boolean	old_verbose;

    while (do_continue) {
	do_continue = rsp_ProcessorStep();
	rsp_UpdateVisual ();
    }

    old_verbose = rsp_SetVerbose (TRUE);
    rsp_UpdateVisual ();
    rsp_SetVerbose (old_verbose);
}

/*
 * private function that implements the instruction classification
 * algorithm. Basically, COP2 op or not, but will correctly handle
 * vload/vstore as SU instructions.
 *
 * Returns TRUE if an SU instruction, or FALSE if a VU instruction.
 *
 */
static boolean
inst_is_scalar(u32 inst)
{
    int	opKey;

    opKey = ExtractOpcode(inst);
    if (opKey == rsp_COP2 && (inst & 0x2000000)) {	/* bit 25 set */
	return (FALSE);
    }

    return(TRUE);
}

/*
 * private function that computes a mask of the destination Vregs
 * Basically, COP2 op or not, but will correctly handle
 * vload/vstore as SU instructions.
 *
 * Returns TRUE if an SU instruction, or FALSE if a VU instruction.
 *
 */
static u32
vect_dest_mask(u32 inst)
{
    u32 mask;
    int vd, i;
    static char buf[80];
    extern int debug_vmask;

    mask = 0;

    rsp_DisasmInst( inst, buf, 0 );

    if( buf[0] == 'B' ) 	/* BAD OP */
	return( mask );

    if( buf[0] == 's' ) 	/* store */
	return( mask );

    if( (buf[0] == 'm') && (buf[0] == 'f') ) 	/* Move From */
	return( mask );

    vd = -1;

    for(i=1; buf[i] != '\0'; i++)
	if( buf[i] == '$' )
	    break;
    
    if( buf[i] == '$' && buf[i+1] == 'v' ) {
	vd = buf[i+2] - '0';

	if( isdigit( buf[i+3] ) )
	    vd = 10*vd + (buf[i+3] - '0');
    };

    if( vd < 0 )
	return( mask );
    
    if( (buf[0] == 'l') && (buf[1] == 't') )	/* Transpose */
	mask = 0xff << (vd & 0x18);
    else
	mask = 1 << vd;
    
    if( debug_vmask )
	fprintf(stderr, "VECT_DEST_MASK: vd=%d, mask=0x%08x, inst=<%s>\n", vd, mask, buf );

    return( mask );
	    
}


static boolean branch_inst( u32 );
static boolean ctc2_inst( u32 );
static boolean load_inst( u32 );
static boolean store_inst( u32 );

/*
 * Fetch one (or two) instructions from the cache
 * to execute.
 */
static boolean
rsp_InstFetch(void)
{
    u32		inst1, inst2, tinst;
    u32		vmask1, vmask2;
    char	cmd[32];
    boolean	inst1_type, inst2_type;
    int		new_pc, group_size;
    boolean	inst1_branch;
    static int 	prevDelayClock = 0;
    static int	prev_branch    = 0;

    if (_doingSSTEP)
	return TRUE;

    /*
     * just return if stalled.
     */
    if (rsp_SUIsStalled() || rsp_VUIsStalled()) {
	return FALSE;
    }

    /* using new function which uses memtype argument (Kishor 9/26/94)*/
    inst1 = rsp_ExamineMemory1(rsp_programCounter,rsp_ICACHE_ACCESS);
    inst2 = rsp_ExamineMemory1((rsp_programCounter+4),rsp_ICACHE_ACCESS);

    /*
     * The RSP can execute up to two instructions per clock cycle:
     *
     * zero or one SU instruction and zero or one VU instruction
     * 
     * if the next two instructions are for the same unit, only
     * one instruction group can execute.
     *
     * a branch delay slot is always a one instruction group.
     *
     */

    /*
     * classify each of the instructions:
     */
    inst1_type = inst_is_scalar(inst1);
    inst2_type = inst_is_scalar(inst2);

    inst1_branch = branch_inst(inst1);


    /*
     * build an instruction group to execute.
     * if we are in a branch delay, only allow one instruction.
     */
    if ( prev_branch ) {	/* Always single issue after a branch */
	inst2_type = inst1_type;		/* Single Issue Hack */
    }

    if( (prevDelayClock != rsp_DELAY_INVALID) && /* We are at the target of a taken branch */
	((rsp_programCounter & 0x4) != 0) ) {	/* Destination is not double word aligned */
	inst2_type = inst1_type;		/* Single Issue Hack */
	rsp_ProcessorSlip(TRUE);
    };

    prevDelayClock = delayClock;		


    if( inst2_type != inst1_type ) {		/* Dual issue? */
	vmask1 = vect_dest_mask( inst1 );
	vmask2 = vect_dest_mask( inst2 );
	if( vmask1 & vmask2 )
	    inst2_type = inst1_type;		/* Single Issue Hack */
    };

    if( inst2_type != inst1_type ) {		/* Dual issue? */
	if( ctc2_inst(inst1) || ctc2_inst(inst2) )	/* TOO general, but OK for now */
	    inst2_type = inst1_type;		/* Single Issue Hack */
    };


    if( inst2_type != inst1_type )		/* Dual issue? */
	prev_branch = inst1_branch || branch_inst(inst2); /* Are either a branch? */
    else
	prev_branch = inst1_branch;		 /* Is single inst. a branch? */


    if (!(rsp_SUIsStalled() || rsp_VUIsStalled())) {
	if ( !inst1_branch &&
	    ((inst1_type && !inst2_type) ||
	    (inst2_type && !inst1_type))   ) {
	    rsp_fetchInst.group_size = 2;
	    if (inst1_type) {
		rsp_fetchInst.instS = inst1;
		rsp_fetchInst.instV = inst2;
		rsp_fetchInst.pcS = rsp_programCounter;
		rsp_fetchInst.pcV = rsp_programCounter+4;
		rsp_fetchInst.validV = TRUE;
		rsp_fetchInst.validS = TRUE;
		rsp_fetchInst.Vfirst = FALSE;
		rsp_fetchInst.SisLoad = load_inst(inst1);
		rsp_fetchInst.SisStore = store_inst(inst1);
	    } else {
		rsp_fetchInst.instV = inst1;
		rsp_fetchInst.instS = inst2;
		rsp_fetchInst.pcV = rsp_programCounter;
		rsp_fetchInst.pcS = rsp_programCounter+4;
		rsp_fetchInst.validV = TRUE;
		rsp_fetchInst.validS = TRUE;
		rsp_fetchInst.Vfirst = TRUE;
		rsp_fetchInst.SisLoad = load_inst(inst2);
		rsp_fetchInst.SisStore = store_inst(inst2);
	    }
	} else {
	    rsp_fetchInst.group_size = 1;
	    if (inst1_type) {
		rsp_fetchInst.instS = inst1;
		rsp_fetchInst.pcS = rsp_programCounter;
		rsp_fetchInst.validS = TRUE;
		rsp_fetchInst.validV = FALSE;
		rsp_fetchInst.SisLoad = load_inst(inst1);
		rsp_fetchInst.SisStore = store_inst(inst1);
	    } else {
		rsp_fetchInst.instV = inst1;
		rsp_fetchInst.pcV = rsp_programCounter;
		rsp_fetchInst.validV = TRUE;
		rsp_fetchInst.validS = FALSE;
		rsp_fetchInst.SisLoad = FALSE;
		rsp_fetchInst.SisStore = FALSE;
	    }
	}

	/* lock any scalar registers for moves/loads: */
	if (rsp_fetchInst.validS) {
	    if (load_inst(rsp_fetchInst.instS)) {
		rsp_SUAddLocks(rsp_fetchInst.instS);
	    }
	}

    }

    return TRUE;
}

static boolean
branch_inst( u32 inst )
{
    char cmd[1024];

    rsp_DisasmInst(inst, cmd, 0);

    return( (cmd[0] == 'b') || (cmd[0] == 'j') );
}


static boolean
ctc2_inst( u32 inst )
{
    char cmd[1024];

    rsp_DisasmInst(inst, cmd, 0);

    return( (cmd[0] == 'c') &&
/*	    (cmd[1] == 't') &&		/* Maybe allow cfc2 also */
	    (cmd[2] == 'c') &&
	    (cmd[3] == '2'));
}

static boolean
load_inst( u32 inst )
{
    char cmd[1024];

    rsp_DisasmInst(inst, cmd, 0);

    if ((strncmp(cmd, "lb", 2) == 0) ||
	(strncmp(cmd, "lh", 2) == 0) ||
	(strncmp(cmd, "lw", 2) == 0) ||
	(strncmp(cmd, "ls", 2) == 0) ||
	(strncmp(cmd, "ll", 2) == 0) ||
	(strncmp(cmd, "ld", 2) == 0) ||
	(strncmp(cmd, "lq", 2) == 0) ||
	(strncmp(cmd, "lr", 2) == 0) ||
	(strncmp(cmd, "lp", 2) == 0) ||
	(strncmp(cmd, "luv", 3) == 0) ||
	(strncmp(cmd, "lf", 2) == 0) ||
	(strncmp(cmd, "lw", 2) == 0) ||
	(strncmp(cmd, "lt", 2) == 0) ||
	(strncmp(cmd, "mf", 2) == 0) ||
	(strncmp(cmd, "mt", 2) == 0) ||
	(strncmp(cmd, "cf", 2) == 0) ||
	(strncmp(cmd, "ct", 2) == 0)) {
	return (TRUE);
    } else {
	return (FALSE);
    }
}

static boolean
store_inst( u32 inst )
{
    char cmd[1024];

    rsp_DisasmInst(inst, cmd, 0);

    if ((strncmp(cmd, "sb", 2) == 0) ||
	(strncmp(cmd, "sh", 2) == 0) ||
	(strncmp(cmd, "sw", 2) == 0) ||
	(strncmp(cmd, "ss", 2) == 0) ||
	(strncmp(cmd, "sl", 2) == 0) ||
	(strncmp(cmd, "sd", 2) == 0) ||
	(strncmp(cmd, "sq", 2) == 0) ||
	(strncmp(cmd, "sr", 2) == 0) ||
	(strncmp(cmd, "sp", 2) == 0) ||
	(strncmp(cmd, "suv", 3) == 0) ||
	(strncmp(cmd, "sf", 2) == 0) ||
	(strncmp(cmd, "sw", 2) == 0) ||
	(strncmp(cmd, "st", 2) == 0) ||
	(strncmp(cmd, "mf", 2) == 0) ||
	(strncmp(cmd, "mt", 2) == 0) ||
	(strncmp(cmd, "cf", 2) == 0) ||
	(strncmp(cmd, "ct", 2) == 0)) {
	return (TRUE);
    } else {
	return (FALSE);
    }
}

/*
 * Execute an instruction group. (fetched on the previous
 * clock cycle)
 */
static boolean
rsp_InstExec(void)
{
    char	cmd[32];
    int		new_pc;

    /*
     * just return if stalled.
     */
    if (rsp_VUIsStalled()) {
	return FALSE;
    }

    /*
     * check for SU stalls before executing:
     */
    if (rsp_fetchInst.validS) {
	if (rsp_SUCheckLocks(rsp_fetchInst.instS)) {
	    rsp_Verbose(stderr,"SU is stalled!\n");
	    return FALSE;
	}
    }

    /*
     * move previously-fetched instruction to execute..
     */
    rsp_LoadStoreSlip[1] = rsp_LoadStoreSlip[0];
    rsp_LoadStoreSlip[0] = rsp_execInst.SisLoad;
    bcopy((char *)&rsp_fetchInst, (char *)&rsp_execInst, 
	  sizeof(rsp_instGroup_t));

/*
    fprintf(stderr,"SU load/store: last 2 instructions %s %s...\n",
	    (rsp_LoadStoreSlip[0]) ? "TRUE" : "FALSE",
	    (rsp_LoadStoreSlip[1]) ? "TRUE" : "FALSE");

    fprintf(stderr,"[%08x] SisStore = %s\n",
	    rsp_programCounter,(rsp_execInst.SisStore) ? "TRUE" : "FALSE");
*/
    if (rsp_execInst.SisStore && rsp_LoadStoreSlip[1]) {
	rsp_Verbose(stderr,"SU load/store stall!\n");
	rsp_ProcessorSlip(TRUE);
    }

    /* 
     * execute the instruction group.
     */
    new_pc = rsp_programCounter;
    if (rsp_execInst.group_size == 1) {
	if (rsp_execInst.validS) {
	    rsp_DisasmInst(rsp_execInst.instS, cmd, new_pc);
	    rsp_Verbose(stderr,"0x%08x - 0x%08x:    %s\n",
		    rsp_clock, rsp_programCounter, cmd);
	    if (vtout) {
		rsp_fprintf(vtout,"0x%08x - 0x%08x:    %s\n",
			    rsp_clock, rsp_programCounter, cmd);
	    }
	    rsp_SUExec(rsp_execInst.instS, rsp_execInst.pcS);
	    new_pc += 4;
	} else if (rsp_execInst.validV) {
	    rsp_DisasmInst(rsp_execInst.instV, cmd, new_pc);
	    rsp_Verbose(stderr,"0x%08x - 0x%08x:    \t\t\t%s\n",
		    rsp_clock, rsp_programCounter, cmd);
	    if (vtout) {
		rsp_fprintf(vtout,"0x%08x - 0x%08x:    %s\n",
			    rsp_clock, rsp_programCounter, cmd);
	    }
	    rsp_VUExec(rsp_execInst.instV, rsp_execInst.pcV);
	    new_pc += 4;
	} else {
	    /* error */
	}
    } else if (rsp_execInst.group_size == 2) {

	rsp_DisasmInst(rsp_execInst.instS, cmd, rsp_execInst.pcS);
	rsp_Verbose(stderr,"0x%08x - 0x%08x:    %s\t",
		rsp_clock, rsp_programCounter, cmd);

	if (vtout) {
	    rsp_fprintf(vtout,"0x%08x - 0x%08x:    %s\t",
			rsp_clock, rsp_programCounter, cmd);
	}

	rsp_DisasmInst(rsp_execInst.instV, cmd, rsp_execInst.pcV);
	rsp_Verbose(stderr,"%s\n",cmd);

	if (vtout) {
	    rsp_fprintf(vtout,"%s\n",cmd);
	}

	if (rsp_execInst.Vfirst) {
	    rsp_VUExec(rsp_execInst.instV, rsp_execInst.pcV);
	    new_pc = (new_pc + 4) & 0xffc;
	    rsp_programCounter = 0x04001000 + (new_pc& 0xffc);
	    rsp_SUExec(rsp_execInst.instS, rsp_execInst.pcS);
	    new_pc = (new_pc + 4) & 0xffc;
	} else {
	    rsp_SUExec(rsp_execInst.instS, rsp_execInst.pcS);
	    new_pc = (new_pc + 4) & 0xffc;
	    rsp_programCounter = 0x04001000 + (new_pc& 0xffc);
	    rsp_VUExec(rsp_execInst.instV, rsp_execInst.pcV);
	    new_pc = (new_pc + 4) & 0xffc;
	}
    }

    /*
     * the PC is either updated correctly (either 1 or 2 instructions
     * executed), or updated by a branch target.
     */
    if (rsp_clock >= delayClock) {
	rsp_programCounter = tempPC;
	delayClock = rsp_DELAY_INVALID;
	/* kill fetched instruction */
	bzero((char *)&rsp_fetchInst, sizeof(rsp_instGroup_t));
    } else {
	rsp_programCounter = 0x04001000 + (new_pc& 0xffc);
    }

    return(TRUE);
}

/*
 * this function sets the value when a jump/branch
 * needs to set the PC.
 */
void
rsp_PCSet(u32 addr, int clockDelay)
{
    tempPC = 0x04001000 + (addr & 0xffc);
    delayClock = rsp_clock + clockDelay;
}

/*
 * This function maintains a 'stall' table for the scalar registers.
 * If, when we go to use any SU register, it's 'count' value is > 0,
 * then we must stall untill it counts down to zero.
 *
 * This proc runs every clock tick, doing the count down. It also manages
 * a 'waiting' queue, in case 2 instructions in a row lock a register.
 *
 * This stall machinery is disabled when VUZeroPipe is TRUE, meaning
 * we are running in an 'instruction boundary' mode.
 */
static boolean
rsp_SUStaller(void)
{
    int		i;

    for (i=0; i<32; i++) {
	if (rsp_SURegStalls[i].count > 0) {
	    rsp_SURegStalls[i].count--;	/* decrement lock */
/*
	    if (rsp_SURegStalls[i].count == 0)
		rsp_Verbose(stderr,"SU : un-locking register $%d\n",i);
*/
	}

	if (rsp_SURegStalls[i].count == 0 && rsp_SURegStalls[i].waiting > 0) {
/*
	    rsp_Verbose(stderr,"SU : locking register $%d\n",i);
*/
	    rsp_SURegStalls[i].count = 4;	/* reset lock */
	    rsp_SURegStalls[i].waiting--;	/* decrement wait queue */
	}
    }

    return(TRUE);
}

/* lock an SU register */
boolean
rsp_SULockReg(int reg)
{
    if (VUZeroPipe) {
	/* don't allow locks or stalls */
	rsp_SURegStalls[reg].count = 0;
    } else {
	if (rsp_SURegStalls[reg].count > 0) {
	    rsp_SURegStalls[reg].waiting++; /* add to wait queue */
	} else {
	    /*
	       rsp_Verbose(stderr,"SU : locking register $%d\n",reg);
	       */
	    rsp_SURegStalls[reg].count = 4;
	}
    }
}

/* is this SU register locked? */
boolean
rsp_SURegIsLocked(int reg)
{
    return(rsp_SURegStalls[reg].count);
}

static boolean
rsp_SUAddLocks(u32 inst)
{
    int		opKey, rt;

    opKey = ExtractOpcode(inst);

    /* regular SU loads */
    if (opKey >= rsp_LB && opKey <= rsp_LHU) {
	rt = ExtractBits(inst, 20, 16);
	rsp_SULockReg(rt);
    }

    /* cop0 moves */
    if (opKey == rsp_COP0) {
	opKey = ExtractBits(inst, 25, 21);	/* what kind of op */
	if (opKey == 0x04) {	/* only lock MTC0 */
	    rt = ExtractBits(inst, 20, 16);
	    rsp_SULockReg(rt);
	}
    }

    /* VU loads and moves handled elsewhere...  */

    return(TRUE);
}


static boolean
rsp_SUCheckLocks(u32 inst)
{
    int		rs = -1, rd = -1;
    u32		opKey;

    if (VUZeroPipe) {
	/* don't allow locks or stalls */
	return FALSE;
    }

    opKey = ExtractOpcode(inst);
    switch (opKey) {
      case rsp_SPECIAL:
	opKey = ExtractBits(inst, 5, 0);
	if (opKey == rsp_BREAK) {
	    /* do nothing */
	} else if (opKey >= rsp_JR && opKey <= rsp_JALR) {
	    if (opKey == rsp_JR) {
		rs = ExtractBits(inst, 25, 21);
	    }
	} else {
	    rs = ExtractBits(inst, 25, 21);
	    rd = ExtractBits(inst, 20, 16);
	}
	break;

      case rsp_REGIMM:
	/* no registers to check */
	break;
	
      case rsp_COP0:	/* MFC0/MTC0 BC0T/BC0F */
	break;

      case rsp_COP2:	/* MFC2/MTC2 CFC2/CTC2 */
	break;

      default:
	if (opKey >= rsp_J && opKey <= rsp_BGTZ)
	    /* no registers to check */
	    ;
	else if (opKey >= rsp_ADDI && opKey <= rsp_LUI)
	    rs = ExtractBits(inst, 25, 21);
	else if (opKey >= rsp_LB && opKey <= rsp_LHU)
	    /* don't check for loads */
	    ;
	else if (opKey >= rsp_SB && opKey <= rsp_SW)
	    /* don't check for stores */
	    ;
	else if (opKey >= rsp_LWC2 && opKey <= rsp_SWC2)
	    /* don't check for VU load/stores */
	    ;
	break;
    }

    if (rs != -1) {
	if (rsp_SURegIsLocked(rs))
	    return(TRUE);
    }

    if (rd != -1) {
	if (rsp_SURegIsLocked(rd))
	    return(TRUE);
    }

    return(FALSE);
}