Virtuoso_0.13um_Ver2.1a.1.map
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# TSMC layout layer mapping file VER 2.1a.1
# FOR TSMC 0.13UM PROCESSES
#
# 03/20/2000 VER 1.0a by T.C.Chiang
# 1) add dummy metal layers
#
# 03/30/2000 VER 1.0b by T.C.Chiang
# 1) add DMN2V/DMP2V
#
# 08/25/2000 VER 1.0c by T.C.Chiang
# 1) add metal slot layers, FUSE(95), PMDMY(106), RHRIDMY(120), VARDMY(143), INDDMY(144)
# 2) add ESD1DMY(145),ESD2DMY(146),ESD3DMY(147),CTMDMY(148), POLYG pin (149)
# 3) add dummy metal insertion blockage layer DMEXCL(150), ALPAD(246)
# 4) modified EM_DRAM used layer(96-105)
# 5) remove unused layer HVPLDD/HVNLDD/HVII/PTDIODE/OD1/FLG1/FLG2/Poly1/HVI
# 6) rename LPR to HRI
#
# 01/11/2001 VER 1.1a by T.C.Chiang
# 1) add NHV(14), SLTEXCL(79), TMVID(80), LMARK(109), RHDMY(117), VIAD(167), MD(168),
# CBD(169), UBM(170)
# 2) remove unused layer ALPAD, VCDUMMY, CTM2, CTM3, CTM4, CTM5, CTM6, CTM8
# 3) rename ESEXCL to DMSRM, CTM7 to CTM
#
# 02/12/2001 VER 1.1b by T.C.Chiang
# 1) add IP tagging used layer IP(63;63), MD pin(159), PADDMY(160)
#
# 05/31/2001 VER 1.1c by Daniel Yan
# 1) Recover M1_PO, M1_OD SymContactDevice
#
# 10/12/2001 VER 1.1d by Daniel Yan
# 1) Add CAP1TDMY(78) to define capacitor for Emb1TRAM cell array
# 2) Add RFDUMMY(161) to define RF devices
# 3) Add SEALRING(162) to for special logic operations
#
# 01/02/2002 VER 1.2a by Daniel Yan
# 1) Add LVID(73) for Low-Vt IDentificaion layer
# 2) Add VIAEXCL(153;1~9) for blockage in VIA insertion
# 3) Add 154;0~7 for embflash process
# FLASH(154;0), MW(154;1), FLGT(154;2), MPOL(154;3), HVII(154;4), HVNW(154;5),
# HVPW(154;6), TOPMCON(154;7)
# 4) Remove old embflash reserved layers:
# HVPF(81), HVNW(82), HNVT(83), VTEH(84), HPVT(85), TIM(86)
# 5) Rename
# VT1MN => VTL_N, VT1MP => VTL_P, VT2MN => VTH_N, VT2MP => VTH_P
# 6) Remove ESD(27), please refer to ESD3DMY(147)
#
# 01/30/2002 VER 1.2b by lwhung
# 1) Add VARDMY(143;1), VARDMY(143;2), VARDMY(143;3) to define RF MOSCAP_G3, MOSCAP_G6, xjvar device
#
# 04/04/2002 VER 1.3a by lwhung
# 1) Add CSRDMY(166;0) for chip corner stress relief pattern layer
# 2) Add DIFF dummy (6;1) and POLYG dummy (17;1)
# 3) Add OD blockage ODBLK(150;20), POLY blockage POBLK(150;21)
# 4) Rename FUSE(95) to FW(95)
# 5) Add DIFF drain(6;3) layer for RF MOS to recognize Drain
# 6) Add LW(109;2) for L target window
#
# 05/14/2002 VER 1.3b by lwhung
# 1) Add VIAP(151), MP(152), MP dummy(152;1), MP slot(152;2) for Additional Thick Metal process
# 2) Add AP(42) for AL PAD.
# 3) Add MOMDMY(155) dummy layer for DRC to cover interdigitated capacitor (IDMOM) region
#
# 05/29/2002 VER 1.3c by lwhung
# 1) Revise LW Virtuoso layer 75 to 105 for reserving 75 for PDK
#
# 07/11/2002 VER 1.4a by lwhung
# 1) Add HVTSRM(60) to cover SRAM cell array
# 2) Remove LW(109;2)
# 3) DSDDMY drawing1~drawing9 (40;1~9) for DSD internal use
# 4) Remove display of additional thick metal process layers
# 5) Remove METAL&VIA(net) and CONT(boundary) and boundary(drawing)
# in tfcDefineLayerProp
#
# 08/02/2002 VER 1.5a by lwhung
# 1) Add CDUDMY(165) for cover CDU pattern in 10um assembly isolation beside seal ring
# 2) Add error (marker;error) (marker;warning) definition in tf file
# 3) Add MWLDMY(154;8), MSLDMY(154;9), M4OPT drawing1(154;10),
# M4OPT drawing2(154;11) for flash process
#
# 08/28/02 VER 1.5b ytpu
# 1) Add LN_CAP(72) for 2.5V Linear NMOS Capacitor N+ implant definition
# 2) Add SRAM_DUMMY(waive;180;0) and SRAM_DUMMY(passgate;180;1) to recognize SRAM pass gate.
# 10/25/02 VER 1.5b.1 ytpu
# 3) Modify layer number of SRAM_DUMMY from 180 to 186;SRAM_DUMMY(waive;186;0) and SRAM_DUMMY(passgate;186;1)
# to recognize SRAM pass gate.
# 4) Add one layer HVNTN(154,datatype:12) for EmbFlash process.
# 5) Disable display number of some layers of technology file as follow:
# PW(2),RW(4),VTP(9),VTN(10),N2V(21),P2V(22),N3V(23),P3V(24),ESDHV(28),BPI(64),TMVID(80),RWDMY(113)
# ,CDMY(118),DNWDMY(126),DMP2V(129),DMN2V(130),PADDMY(160),CELLIMP(44),BC1(45),BC2(46),BTC(47),VCC(48).
# 11/22/2002 ytpu
# 6) Embed flash add four layers and remove one layer:
# Add:
# PSUB(154;13): P_sub for HVNMOS.
# HNVT(154;14): Vt implant area for HVNMOS.
# PO1 (154;15): Area for floating gate contact.
# MCEL(154;16): Define memory cell area.
# Remove:
# TOPMCON(154;7)
# 7) Add layer CBM(88) for capacitor buttom metal layer.
# 8) Resort some layers by mask sequence.
# 01/22/2003 ytpu
# 9) Add layer CB2(86;0;drawing) to CB2 layer ( Dual zone pad's passivation2 opening).
# 01/29/2003 ytpu
# 10) Add layer RFDUMMY(161,1) to define "additional terminal".
# 03/05/2003 ytpu 1.5b.2
# 11) Add some layers of MD layer:MD(dummy,168,1),MD(slot,168,2),DMEXCL(dummyf,150,15)
# SLTEXCL(dummyf,79,15).
# VIAD layer:VIAEXCL(dummy,153,15).
# 12) Modify layer name of SRAM_DUMMY to SRAMDMY.
# 13) Add layers:SRAMDMY(186,allsram,2),SRAMDMY(186,cvss_sram,3),SRAMDMY(186,periphery,4).
#
# 04/15/2003 ytpu 1.5b.3
# 14) Modify all of the Dummy layer name it included DUMMY at the tail of word to DMY.
# 15) Add layer LOGO(158).
# 16) Remove some layers:LNR,DRCDUMMY,POLY2,NHV,COW,PDIMP,VTDN,VTDP,PUIMP.
# 17) Change all layer name of DIFF to OD.
# 18) Add layer POLYG(149,lvs,1)
# 04/29/2003 ytpu 1.5b.4
# 19) Modify the name of NTN layer to NT_N in techfile.
# 07/22/2003 ytpu 2.0a
# 1) Re-added DRCDMY(125).
# 09/17/2003 ytpu
# 2) Added layer WBDMY(183).
# 12/11/2003 ytpu
# 3) Add the pin layers of two layers OD, NW at datatype 6.
# 4) Remove the DRCDMY(125) layer from this version.
# 5) Add the layer DIODMY(119,1,drawing1) for DNW dual diode structure.
# 04/30/2004 ytpu 2.1a
# 1) Add two layers CLDD(92,0) and CAVITY(90,0) for 1TRAM and 1TQ used respectively.
# 05/03/2004
# 2) The layer purpose of the layer number 182 has been expanded to such belows:
# R_rule(182,require,1)
# R_rule(182,recommend,2)
#**************************************************************************************************
# Layer Layer Stream Datatype
# Name Purpose
#--------------------------------------------------------------------
ref drawing 0 0
DNWELL drawing 1 0
# PWELL drawing 2 0
NWELL drawing 3 0
# RWELL drawing 4 0
PLMIDE drawing 5 0
OD drawing 6 0
PDIFF drawing 7 0
NDIFF drawing 8 0
# VTP drawing 9 0
# VTN drawing 10 0
NT_N drawing 11 0
VTL_N drawing 12 0
VTL_P drawing 13 0
OD2 drawing 15 0
OD3 drawing 16 0
POLYG drawing 17 0
# NLDDLV drawing 19 0
# PLDDLV drawing 20 0
# NLDDMV drawing 21 0
# PLDDMV drawing 22 0
# NLDDHV drawing 23 0
# PLDDHV drawing 24 0
PIMP drawing 25 0
NIMP drawing 26 0
# ESD drawing 27 0
# ESDHV drawing 28 0
RPO drawing 29 0
CONT drawing 30 0
METAL1 drawing 31 0
VIA12 drawing 51 0
METAL2 drawing 32 0
VIA23 drawing 52 0
METAL3 drawing 33 0
VIA34 drawing 53 0
METAL4 drawing 34 0
VIA45 drawing 54 0
METAL5 drawing 35 0
VIA56 drawing 55 0
METAL6 drawing 36 0
VIA67 drawing 56 0
METAL7 drawing 37 0
VIA78 drawing 57 0
METAL8 drawing 38 0
VIA89 drawing 58 0
METAL9 drawing 39 0
AP drawing 42 0
PAD drawing 43 0
CB2 drawing 86 0
FW drawing 95 0
LMARK drawing 109 0
IP drawing 63 63
CAP1TDMY drawing 78 0
SEALRING drawing 162 0
LVID drawing 73 0
CDUDMY drawing 165 0
CSRDMY drawing 166 0
LN_CAP drawing 72 0
y6 drawing 213 0
y7 drawing 214 0
#--------------------------------------------------------------------
# For Text layer
NWELL pin 3 6
OD pin 6 6
METAL1 pin 131 0
METAL2 pin 132 0
METAL3 pin 133 0
METAL4 pin 134 0
METAL5 pin 135 0
METAL6 pin 136 0
METAL7 pin 137 0
METAL8 pin 138 0
METAL9 pin 139 0
POLYG pin 149 0
POLYG lvs 149 1
MD pin 159 0
#--------------------------------------------------------------------
# For SRAM process
# CELLIMP drawing 44 0
# BC1 drawing 45 0
# BC2 drawing 46 0
# BTC drawing 47 0
# VCC drawing 48 0
RODMY drawing 49 0
DMSRM drawing 50 0
HVTSRM drawing 60 0
REDUNDMY col 61 1
REDUNDMY row 61 2
SRAMDMY waive 186 0
SRAMDMY passgate 186 1
SRAMDMY allsram 186 2
SRAMDMY cvss_sram 186 3
SRAMDMY periphery 186 4
#--------------------------------------------------------------------
# For MIXED-MODE purpose
# BPI drawing 64 0
VTH_N drawing 67 0
VTH_P drawing 68 0
HRI drawing 70 0
CTM drawing 77 0
CBM drawing 88 0
OD drain 6 3
#--------------------------------------------------------------------
# For NVM process
# OD1 drawing 87 0
# FLG1 drawing 88 0
# FLG2 drawing 89 0
# Poly1 drawing 90 0
# HVI drawing 91 0
# HVNLDD drawing 93 0
# HVPLDD drawing 94 0
#--------------------------------------------------------------------
# For EmbFlash process
FLASH drawing 154 0
MW drawing 154 1
FLGT drawing 154 2
MPOL drawing 154 3
HVII drawing 154 4
HVNW drawing 154 5
HVPW drawing 154 6
MWLDMY drawing 154 8
MSLDMY drawing 154 9
M4OPT drawing1 154 10
M4OPT drawing2 154 11
HVNTN drawing 154 12
PSUB drawing 154 13
HNVT drawing 154 14
PO1 drawing 154 15
MCEL drawing 154 16
#--------------------------------------------------------------------
# For EM_DRAM process
DNW2 drawing 96 0
CW drawing 97 0
P1D drawing 98 0
P1W drawing 99 0
CLDD drawing 92 0
BLC drawing 101 0
CROWN drawing 102 0
P3 drawing 103 0
P1C drawing 104 0
DPITCH drawing 105 0
CAVITY drawing 90 0
#--------------------------------------------------------------------
# For P&R purpose
OVERLAP drawing 107 0
prBoundary drawing 108 0
#-------------------------------------------------------------------
# Dummy layer for LVS/DRC checking
PMDMY drawing 106 0
BJTDMY drawing 110 0
PSUB2 drawing 111 0
HOTWL drawing 112 0
# RWDUMMY drawing 113 0
NWDMY drawing 114 0
RPDMY drawing 115 0
RMDMY drawing 116 0
RHDMY drawing 117 0
# CDUMMY drawing 118 0
DIODMY drawing 119 0
DIODMY drawing1 119 1
RHRIDMY drawing 120 0
EXCL drawing 121 0
SDI drawing 122 0
DPDMY drawing 123 0
PLDMY drawing 124 0
# DNWDUMMY drawing 126 0
text drawing 127 0
# DMP2V drawing 129 0
# DMN2V drawing 130 0
VARDMY drawing 143 0
VARDMY drawing1 143 1
VARDMY drawing2 143 2
VARDMY drawing3 143 3
INDDMY drawing 144 0
ESD1DMY drawing 145 0
ESD2DMY drawing 146 0
ESD3DMY drawing 147 0
CTMDMY drawing 148 0
# TMVID drawing 80 0
# PADDMY drawing 160 0
RFDMY drawing 161 0
RFDMY drawing1 161 1
MOMDMY drawing 155 0
LOGO drawing 158 0
#--------------------------------------------------------------------
# DRC error report
marker error 163 0
marker warning 164 0
#--------------------------------------------------------------------
# For solder Bump and RDL layer
VIAD drawing 167 0
MD drawing 168 0
CBD drawing 169 0
UBM drawing 170 0
#--------------------------------------------------------------------
# For Blockage layer
METAL1 boundary 171 0
METAL2 boundary 172 0
METAL3 boundary 173 0
METAL4 boundary 174 0
METAL5 boundary 175 0
METAL6 boundary 176 0
METAL7 boundary 177 0
METAL8 boundary 178 0
METAL9 boundary 179 0
VIA12 boundary 191 0
VIA23 boundary 192 0
VIA34 boundary 193 0
VIA45 boundary 194 0
VIA56 boundary 195 0
VIA67 boundary 196 0
VIA78 boundary 197 0
VIA89 boundary 198 0
#--------------------------------------------------------------------
# For dummy metal
OD dummy 6 1
POLYG dummy 17 1
METAL1 dummy 31 1
METAL2 dummy 32 1
METAL3 dummy 33 1
METAL4 dummy 34 1
METAL5 dummy 35 1
METAL6 dummy 36 1
METAL7 dummy 37 1
METAL8 dummy 38 1
METAL9 dummy 39 1
MD dummy 168 1
#--------------------------------------------------------------------
# For metal slot
METAL1 slot 31 2
METAL2 slot 32 2
METAL3 slot 33 2
METAL4 slot 34 2
METAL5 slot 35 2
METAL6 slot 36 2
METAL7 slot 37 2
METAL8 slot 38 2
METAL9 slot 39 2
MD slot 168 2
#--------------------------------------------------------------------
# For dummy metal insertion blockage layer
DMEXCL dummy1 150