cs.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: cs.v,v 1.7 2003/01/24 23:07:36 berndt Exp $
/////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: cs
// description: Top level module for command shuffle unit
//
//
// designer: Mike M. Cai 7/19/94
//
/////////////////////////////////////////////////////////////////////////
`timescale 100 ps / 100 ps
module cs( // outputs
tile_addr, cs_tc_data, we_tile_size, we_tile_attr,
cs_ew_data, cs_ew_newprim,
cs_xbus_req, // valid if 10 or more words are avail.
cmd, start_prim, attr_valid,
cmd_busy,
//inputs
xbus_cs_data, xbus_cs_valid, ew_cs_busy, ms_busy,
rel_sync_tile, rel_sync_pipe, rel_sync_full, rel_sync_load,
texel_size, copy_fill,
reset_l, clk, start_gclk);
output [2:0] tile_addr;
output [47:0] cs_tc_data;
output we_tile_size, we_tile_attr;
output [63:0] cs_ew_data;
output cs_ew_newprim;
output cs_xbus_req;
output [5:0] cmd;
output start_prim, attr_valid;
output cmd_busy;
input [63:0] xbus_cs_data;
input xbus_cs_valid;
input ew_cs_busy, ms_busy;
input rel_sync_tile, rel_sync_pipe, rel_sync_full, rel_sync_load;
input [1:0] texel_size;
input copy_fill;
input reset_l, clk, start_gclk;
// resetb
// wire resetb;
// csclk signals
wire [4:0] wr_adrs;
wire cs_xbus_req;
wire empty;
wire cmd_busy;
wire [5:0] words_fifo;
// csgclk signals
wire [2:0] tile_addr;
wire [47:0] cs_tc_data;
wire we_tile_size, we_tile_attr;
wire [63:0] cs_ew_data;
wire cs_ew_newprim;
wire [5:0] read_adrs;
wire [4:0] rm_addr, rl_addr;
wire [5:0] cmd;
wire start_prim, attr_valid;
// Ram
wire [63:0] fifo_out;
csclk clklogic( // outputs
.wr_adrs(wr_adrs),
.cs_xbus_req(cs_xbus_req),
.empty(empty), .cmd_busy(cmd_busy),
.words_fifo(words_fifo),
// inputs
.xbus_valid(xbus_cs_valid),
.read_adrs(read_adrs),
.clk(clk), .reset_l(reset_l)
);
csgclk gclklogic( // outputs
.tile_addr(tile_addr),
.cs_tc_data(cs_tc_data),
.we_tile_size(we_tile_size),
.we_tile_attr(we_tile_attr),
.cs_ew_data(cs_ew_data),
.cs_ew_newprim(cs_ew_newprim),
.read_adrs(read_adrs),
.rm_addr(rm_addr),
.rl_addr(rl_addr),
.cmd(cmd),
.start_prim(start_prim),
.attr_valid(attr_valid),
// inputs
.fifo_out(fifo_out),
.texel_size(texel_size),
.words_fifo(words_fifo),
.empty(empty),
.rel_sync_tile(rel_sync_tile),
.rel_sync_pipe(rel_sync_pipe),
.rel_sync_full(rel_sync_full),
.rel_sync_load(rel_sync_load),
.ew_cs_busy(ew_cs_busy),
.ms_busy(ms_busy),
.copy_fill(copy_fill),
.reset_l(reset_l), .clk(clk), .start_gclk(start_gclk)
);
wire clkb = ~clk; // XXX invert clock to remove the
// pipeline delay of the SRAM
cs_buf msbbuf ( .wen(xbus_cs_valid),
.clk(clkb),
.ra(rm_addr),
.wa(wr_adrs),
.di(xbus_cs_data[63:32]),
.dout(fifo_out[63:32])
);
cs_buf lsbbuf( .wen(xbus_cs_valid),
.clk(clkb),
.ra(rl_addr),
.wa(wr_adrs),
.di(xbus_cs_data[31:0]),
.dout(fifo_out[31:0])
);
endmodule // cs