rsp_ctrace.vh
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rsp_ctrace.h
Port from rsp reality test: rsp_regr.h
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/************************************************
* Path definitions
************************************************/
`define rsp_path vsim.bb.bcp.rsp
`define NEWVU 1
`define tr vsim.rsp_ctrace
`define SRpath `rsp_path.su.sudp.surfilei
`define vu_path `rsp_path.vu
`define VRpath `vu_path.vdpregfile_i
`define vumemb_0 `VRpath.memsl0hi.vubuf.ram_prim
`define vumemb_1 `VRpath.memsl0lo.vubuf.ram_prim
`define vumemb_2 `VRpath.memsl1hi.vubuf.ram_prim
`define vumemb_3 `VRpath.memsl1lo.vubuf.ram_prim
`define vumemb_4 `VRpath.memsl2hi.vubuf.ram_prim
`define vumemb_5 `VRpath.memsl2lo.vubuf.ram_prim
`define vumemb_6 `VRpath.memsl3hi.vubuf.ram_prim
`define vumemb_7 `VRpath.memsl3lo.vubuf.ram_prim
`define vumemb_8 `VRpath.memsl4hi.vubuf.ram_prim
`define vumemb_9 `VRpath.memsl4lo.vubuf.ram_prim
`define vumemb_a `VRpath.memsl5hi.vubuf.ram_prim
`define vumemb_b `VRpath.memsl5lo.vubuf.ram_prim
`define vumemb_c `VRpath.memsl6hi.vubuf.ram_prim
`define vumemb_d `VRpath.memsl6lo.vubuf.ram_prim
`define vumemb_e `VRpath.memsl7hi.vubuf.ram_prim
`define vumemb_f `VRpath.memsl7lo.vubuf.ram_prim
/*******************************************
* IMEM and DMEM and reg pointers
*******************************************/
`define IMEM `rsp_path.imem.ram_prim
`define DMEM0 `rsp_path.dmemx2.dmemLow.ram_prim0
`define DMEM1 `rsp_path.dmemx2.dmemLow.ram_prim1
`define DMEM2 `rsp_path.dmemx2.dmemLow.ram_prim2
`define DMEM3 `rsp_path.dmemx2.dmemLow.ram_prim3
`define DMEM4 `rsp_path.dmemx2.dmemLow.ram_prim4
`define DMEM5 `rsp_path.dmemx2.dmemLow.ram_prim5
`define DMEM6 `rsp_path.dmemx2.dmemLow.ram_prim6
`define DMEM7 `rsp_path.dmemx2.dmemLow.ram_prim7
`define DMEM8 `rsp_path.dmemx2.dmemHigh.ram_prim0
`define DMEM9 `rsp_path.dmemx2.dmemHigh.ram_prim1
`define DMEM10 `rsp_path.dmemx2.dmemHigh.ram_prim2
`define DMEM11 `rsp_path.dmemx2.dmemHigh.ram_prim3
`define DMEM12 `rsp_path.dmemx2.dmemHigh.ram_prim4
`define DMEM13 `rsp_path.dmemx2.dmemHigh.ram_prim5
`define DMEM14 `rsp_path.dmemx2.dmemHigh.ram_prim6
`define DMEM15 `rsp_path.dmemx2.dmemHigh.ram_prim7
`define r1 `rsp_path.su.sudp.surfilei.mem1.z
`define r30 `rsp_path.su.sudp.surfilei.mem30.z
`define r31 `rsp_path.su.sudp.surfilei.mem31.z
/************************************************
* Key signals
************************************************/
`define CLK `rsp_path.clk
`define Break `rsp_path.io_mem_dma.mem_dma.broke
`define Halt `rsp_path.io_mem_dma.halt
`define Reset_l `rsp_path.reset_l
/******************************************
* TimeOut Count values
******************************************/
`ifdef LARGE_TIMEOUT
`define TIMEOUT_CNT 24'h3fffff
`else
`define TIMEOUT_CNT 24'h80000
`endif
`define TIMEOUT_CNT_SS 24'h6000
/*****************************************
* Trace Depth
******************************************/
`define VR_TRACE_DEPTH 256
`ifdef LARGE_TRACE_BUFFER
`define SU_TRACE_DEPTH 100000
`define DM_TRACE_DEPTH 100000
`else
`define SU_TRACE_DEPTH 2048
`define DM_TRACE_DEPTH 2048
`endif