sp.vh
1.37 KB
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`include "rcp.vh"
parameter
SP_REG_DATA_SIZE = 32,
SP_REG_ADDRESS_SIZE = 3,
SP_MEM_ADDRESS_SIZE = 9,
SP_MEM_MASK_SIZE = 2,
SP_PC_SIZE = 10,
SP_PC_OFFSET = 2,
SP_DEVICE_SIZE = 2,
SP_DEVICE_OFFSET = 18,
SP_BIST_FAIL_SIZE = 4,
SP_SIGNAL_SIZE = 8;
parameter
SP_DEVICE_MEM = 0,
SP_DEVICE_CP0 = 1,
SP_DEVICE_REG = 2;
parameter
SP_DMA_MASTER_ADDRESS_SIZE = SP_MEM_ADDRESS_SIZE,
SP_DMA_SLAVE_ADDRESS_SIZE = DRAM_ADDRESS_SIZE - DMA_OFFSET_SIZE,
SP_DMA_SKIP_SIZE = 9,
SP_DMA_COUNT_SIZE = 8,
SP_DMA_LENGTH_SIZE = 9,
SP_DMA_MAX_BLOCK = 4'hf;
parameter
SP_CMD_ADDRESS_SIZE = DRAM_ADDRESS_SIZE - DMA_OFFSET_SIZE,
SP_CMD_LENGTH_SIZE = DMA_LENGTH_SIZE - DMA_OFFSET_SIZE,
SP_CMD_IO_ADDRESS_SIZE = 2;
// DMA register addresses
parameter
SP_BANK_DMA = 0,
SP_BANK_STATUS = 1,
SP_BANK_CMD = 2,
SP_BANK_COUNTER = 3;
parameter
SP_DMA_MASTER_ADDRESS = 0,
SP_DMA_SLAVE_ADDRESS = 1,
SP_DMA_READ_LENGTH = 2,
SP_DMA_WRITE_LENGTH = 3,
SP_DMA_STATUS = 4,
SP_DMA_FULL = 5,
SP_DMA_BUSY = 6,
SP_DMA_SEMAPHORE = 7;
parameter
SP_REG_PC = 0,
SP_REG_BIST = 1;
parameter
SP_CMD_START_ADDRESS = 0,
SP_CMD_END_ADDRESS = 1,
SP_CMD_CURRENT_ADDRESS = 2,
SP_CMD_STATUS = 3,
SP_CMD_CLOCK = 4,
SP_CMD_BUSY = 5,
SP_CMD_PIPE_BUSY = 6,
SP_CMD_TMEM_BUSY = 7;