dpxor1021.vmd
1.53 KB
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/**************************************************************/
/* Verilog module of datapath cell DPXOR1021 */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A1 : the input port */
/* INST : the control input port */
/* Z : the output port */
/* ZN : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpxor1021(A1, INST, Z, ZN);
parameter WORDSIZE = 8, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] A1;
input INST;
output [WORDSIZE-1:0] Z, ZN;
function [WORDSIZE-1:0] x_or;
input [WORDSIZE-1:0] A1;
input INST;
integer i;
begin
i = 0;
for (i = 0; i < WORDSIZE; i = i+1)
x_or[i] = A1[i] ^ INST;
end
endfunction
assign #DELAY Z = x_or(A1, INST),
ZN = ~x_or(A1, INST);
endmodule