// OPENCAD Verilog library : 2001/11/08 : Ver2.0.1
`timescale 1ps/1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module WBROMSMHS2048W16C5N01 (
	DO0,
	DO1,
	DO2,
	DO3,
	DO4,
	DO5,
	DO6,
	DO7,
	DO8,
	DO9,
	DO10,
	DO11,
	DO12,
	DO13,
	DO14,
	DO15,
	TDO0,
	TDO1,
	TDO2,
	TDO3,
	TDO4,
	TDO5,
	TDO6,
	TDO7,
	TDO8,
	TDO9,
	TDO10,
	TDO11,
	TDO12,
	TDO13,
	TDO14,
	TDO15,
	A0,
	A1,
	A2,
	A3,
	A4,
	A5,
	A6,
	A7,
	A8,
	A9,
	A10,
	BE,
	CSB,
	TA0,
	TA1,
	TA2,
	TA3,
	TA4,
	TA5,
	TA6,
	TA7,
	TA8,
	TA9,
	TA10,
	TBE,
	BUNRI,
	TEST
);
output DO0;
output DO1;
output DO2;
output DO3;
output DO4;
output DO5;
output DO6;
output DO7;
output DO8;
output DO9;
output DO10;
output DO11;
output DO12;
output DO13;
output DO14;
output DO15;
output TDO0;
output TDO1;
output TDO2;
output TDO3;
output TDO4;
output TDO5;
output TDO6;
output TDO7;
output TDO8;
output TDO9;
output TDO10;
output TDO11;
output TDO12;
output TDO13;
output TDO14;
output TDO15;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
input A8;
input A9;
input A10;
input BE;
input CSB;
input TA0;
input TA1;
input TA2;
input TA3;
input TA4;
input TA5;
input TA6;
input TA7;
input TA8;
input TA9;
input TA10;
input TBE;
input BUNRI;
input TEST;

parameter BIT=16;
parameter WORD=2048;
parameter ADD_BIT=11;

reg[BIT-1:0] DO,TDO;
reg [BIT-1:0] tmp_DO,tmp_TDO;
wire[ADD_BIT-1:0] A,TA;
reg pre_BE,pre_TBE;
reg csb;
wire pre_csb;
reg [BIT-1:0] rom_data[0:WORD-1];

`ifdef NEC_RTL_SIM
    parameter tACC = 3562 ; // Dummy value in Read mode
`endif // NEC_RTL_SIM

`ifdef NEC_RTL_SIM
`else
    reg notifier_r;
    reg notifier_rt;
    reg notifier_rp;
`endif // NEC_RTL_SIM

`ifdef NEC_RTL_SIM
    initial begin
        PrintRTLMsg;
    end
`endif // NEC_RTL_SIM

integer mode,pre_mode;

	buf(_A0,A0);
	buf(_A1,A1);
	buf(_A2,A2);
	buf(_A3,A3);
	buf(_A4,A4);
	buf(_A5,A5);
	buf(_A6,A6);
	buf(_A7,A7);
	buf(_A8,A8);
	buf(_A9,A9);
	buf(_A10,A10);
	buf(_BE,BE);
	buf(_CSB,CSB);
	buf(_TA0,TA0);
	buf(_TA1,TA1);
	buf(_TA2,TA2);
	buf(_TA3,TA3);
	buf(_TA4,TA4);
	buf(_TA5,TA5);
	buf(_TA6,TA6);
	buf(_TA7,TA7);
	buf(_TA8,TA8);
	buf(_TA9,TA9);
	buf(_TA10,TA10);
	buf(_TBE,TBE);
	buf(_BUNRI,BUNRI);
	buf(_TEST,TEST);
	buf(A[0],_A0);
	buf(A[1],_A1);
	buf(A[2],_A2);
	buf(A[3],_A3);
	buf(A[4],_A4);
	buf(A[5],_A5);
	buf(A[6],_A6);
	buf(A[7],_A7);
	buf(A[8],_A8);
	buf(A[9],_A9);
	buf(A[10],_A10);
	buf(TA[0],_TA0);
	buf(TA[1],_TA1);
	buf(TA[2],_TA2);
	buf(TA[3],_TA3);
	buf(TA[4],_TA4);
	buf(TA[5],_TA5);
	buf(TA[6],_TA6);
	buf(TA[7],_TA7);
	buf(TA[8],_TA8);
	buf(TA[9],_TA9);
	buf(TA[10],_TA10);

	buf(_DO0,DO[0]);
	buf(_DO1,DO[1]);
	buf(_DO2,DO[2]);
	buf(_DO3,DO[3]);
	buf(_DO4,DO[4]);
	buf(_DO5,DO[5]);
	buf(_DO6,DO[6]);
	buf(_DO7,DO[7]);
	buf(_DO8,DO[8]);
	buf(_DO9,DO[9]);
	buf(_DO10,DO[10]);
	buf(_DO11,DO[11]);
	buf(_DO12,DO[12]);
	buf(_DO13,DO[13]);
	buf(_DO14,DO[14]);
	buf(_DO15,DO[15]);
	buf(_TDO0,TDO[0]);
	buf(_TDO1,TDO[1]);
	buf(_TDO2,TDO[2]);
	buf(_TDO3,TDO[3]);
	buf(_TDO4,TDO[4]);
	buf(_TDO5,TDO[5]);
	buf(_TDO6,TDO[6]);
	buf(_TDO7,TDO[7]);
	buf(_TDO8,TDO[8]);
	buf(_TDO9,TDO[9]);
	buf(_TDO10,TDO[10]);
	buf(_TDO11,TDO[11]);
	buf(_TDO12,TDO[12]);
	buf(_TDO13,TDO[13]);
	buf(_TDO14,TDO[14]);
	buf(_TDO15,TDO[15]);
	buf(DO0,_DO0);
	buf(DO1,_DO1);
	buf(DO2,_DO2);
	buf(DO3,_DO3);
	buf(DO4,_DO4);
	buf(DO5,_DO5);
	buf(DO6,_DO6);
	buf(DO7,_DO7);
	buf(DO8,_DO8);
	buf(DO9,_DO9);
	buf(DO10,_DO10);
	buf(DO11,_DO11);
	buf(DO12,_DO12);
	buf(DO13,_DO13);
	buf(DO14,_DO14);
	buf(DO15,_DO15);
	buf(TDO0,_TDO0);
	buf(TDO1,_TDO1);
	buf(TDO2,_TDO2);
	buf(TDO3,_TDO3);
	buf(TDO4,_TDO4);
	buf(TDO5,_TDO5);
	buf(TDO6,_TDO6);
	buf(TDO7,_TDO7);
	buf(TDO8,_TDO8);
	buf(TDO9,_TDO9);
	buf(TDO10,_TDO10);
	buf(TDO11,_TDO11);
	buf(TDO12,_TDO12);
	buf(TDO13,_TDO13);
	buf(TDO14,_TDO14);
	buf(TDO15,_TDO15);



parameter data_X={BIT{1'bx}};
parameter data_0={BIT{1'b0}};

/* ---------------------------------------------- timing error */
`ifdef NEC_RTL_SIM
`else
always @ ( notifier_r ) begin
	disable READ_NORMAL;
	DO=data_X;
	tmp_DO=data_X;
end

always @ ( notifier_rt ) begin
	disable READ_TEST;
	#0 disable TDO_0;
	TDO=data_X;
	tmp_TDO=data_X;
end

always @ ( notifier_rp ) begin
    if (pre_csb!==1) begin
        disable READ_NORMAL;
        DO=data_X;
        tmp_DO=data_X;
    end
end
`endif // NEC_RTL_SIM

/* ---------------------------------------------- Nochenge */
event ChMode;

always @ ( _TEST ) begin
    if ( (_TBE!==0)&&(_BUNRI!==0) ) begin
        TDO=data_X;
        tmp_TDO=data_X;
    end
    -> ChMode;
end

always @ ( _BUNRI ) begin
    if ( (_BE!==0)&&(_CSB!==1) ) begin
        DO=data_X;
        tmp_DO=data_X;
    end
    if ( (_TBE!==0)&&(_TEST!==0) ) begin
        TDO=data_X;
        tmp_TDO=data_X;
    end
    -> ChMode;
end

/* ---------------------------------------------- Mode */

always @ ( ChMode ) begin
    casez ( {_BUNRI,_TEST} )
        2'b0? : begin      // normal mode
            if (pre_mode!==1) begin
                mode=1;
                disable READ_TEST;
                // TDO=data_0;
		        DO=data_X;
		        tmp_DO=data_X;
		        TDO_0;
		    end
        end
        2'b10 : begin      // test non-active mode
            mode=2;
            disable READ_NORMAL;
            disable READ_TEST;
            DO=data_X;
            tmp_DO=data_X;
            // TDO=data_0;
			TDO_0;
        end
        2'b11 : begin      // test active mode
            mode=3;
            disable READ_NORMAL;
            DO=data_X;
            tmp_DO=data_X;
            TDO=data_X;
            tmp_TDO=data_X;
        end
/*
        2'b1x : begin      // test mode unknown
            mode=4;
            disable READ_NORMAL;
            disable READ_TEST;
            DO=data_X;
            TDO=data_X;
        end
 */
        default : begin    // mode unknown
            mode=0;
            disable READ_NORMAL;
            disable READ_TEST;
            DO=data_X;
            tmp_DO=data_X;
            TDO=data_X;
            tmp_TDO=data_X;
        end
    endcase
	pre_mode=mode;
end

/* ---------------------------------------------- Normal Mode */
always @ ( _BE or _CSB or A or mode ) begin
    if (mode==1) begin
        casez ( {pre_BE,_BE} )
        2'b01 : begin
            pre_BE=_BE;
			csb=_CSB;
            if (_CSB===0) begin
                if ( A >= WORD ) begin
                    $display($time,,"<Error!!> Address Over. A [%b]",A);
                    $display("\t\t\t -> %m\n");
                    DO=data_X;
                    tmp_DO=data_X;
                end
                begin : READ_NORMAL
            	    tmp_DO=rom_data[A];

`ifdef NEC_RTL_SIM
                    #(tACC) DO=tmp_DO;
`else
                    if (DO===tmp_DO) begin
                        DO=tmp_DO;
                    end
                    else begin
                        if( DO===data_X ) begin
                            DO=tmp_DO;
                        end
                        else begin
			   DO={BIT{1'bx}};
			   #1;
			   if (DO===data_X) begin
			      DO=tmp_DO;
			   end
			end
                    end
`endif // NEC_RTL_SIM

                end
            end
            else if (_CSB===1'bx) begin
                DO=data_X;
                tmp_DO=data_X;
            end
        end
        2'bx1,
        2'b?x : begin
			csb=1'bx;
            if (_CSB!==1) begin
                pre_BE=_BE;
                DO=data_X;
                tmp_DO=data_X;
            end
        end

        endcase
    end
    else if (mode==0) begin
        casez ( {pre_BE,_BE} )
        2'b01,
        2'bx1,
        2'b?x : begin
			csb=1'bx;
            if (_CSB!==1) begin
                pre_BE=_BE;
                DO=data_X;
                tmp_DO=data_X;
            end
        end
        endcase
    end
    pre_BE=BE;
end

/* ---------------------------------------------- Test Mode */
always @ ( _TBE or TA or mode ) begin
    if (mode==3) begin
        casez ( {pre_TBE,_TBE} )
        2'b01 : begin
            pre_TBE=_TBE;
            if ( TA >= WORD ) begin
                $display($time,,"<Error!!> Address Over. TA [%b]",TA);
                $display("\t\t\t -> %m\n");
                TDO=data_X;
                tmp_TDO=data_X;
            end
            begin : READ_TEST
    	        tmp_TDO=rom_data[TA];

`ifdef NEC_RTL_SIM
                #(tACC) TDO=tmp_TDO;
`else
                if (TDO===tmp_TDO) begin
                    TDO=tmp_TDO;
                end
                else begin
                    if( TDO===data_X ) begin
                        TDO=tmp_TDO;
                    end
                    else begin
		       TDO={BIT{1'bx}};
		       #1;
		       if (TDO===data_X) begin
			  TDO=tmp_TDO;
		       end
		    end
                end
`endif // NEC_RTL_SIM

            end
        end
        2'bx1,
        2'b?x : begin
            pre_TBE=_TBE;
            TDO=data_X;
            tmp_TDO=data_X;
        end
        endcase
    end
    else if (mode==0) begin
        casez ( {pre_TBE,_TBE} )
        2'b01,
        2'bx1,
        2'b?x : begin
            pre_TBE=_TBE;
            TDO=data_X;
            tmp_TDO=data_X;
        end
        endcase
    end
    pre_TBE=TBE;
end

/* -------------------- */
task TDO_0;
begin
	TDO=data_0;
	tmp_TDO=data_0;
end
endtask



    buf #1 (pre_csb,csb);

`ifdef NEC_RTL_SIM
`else
    wire check1=((_BUNRI!==1)&&(_CSB!==1));
    wire check2=((_BUNRI!==0)&&(_TEST!==0));
    wire check3=(_BUNRI!==1);
    wire check4=(_BUNRI!==0);
    wire check5=(_TEST!==0);
    wire check6=(_CSB!==1);
    wire check7=((pre_csb!==1)&&(_BUNRI!==1));
`endif // NEC_RTL_SIM

`ifdef NEC_RTL_SIM
`else
    specify
        specparam DMY_SPC=1:1:1;
        specparam CYCLE_TIME=1:1:1;

        $setup(posedge A0, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A0 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A0, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A0 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A1, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A1 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A1, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A1 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A2, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A2 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A2, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A2 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A3, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A3 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A3, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A3 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A4, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A4 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A4, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A4 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A5, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A5 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A5, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A5 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A6, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A6 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A6, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A6 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A7, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A7 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A7, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A7 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A8, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A8 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A8, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A8 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A9, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A9 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A9, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A9 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge A10, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge A10 &&& check1, DMY_SPC, notifier_r);
        $setup(negedge A10, posedge BE &&& check1, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge A10 &&& check1, DMY_SPC, notifier_r);
        $setup(posedge TA0, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA0 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA0, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA0 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA1, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA1 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA1, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA1 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA2, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA2 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA2, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA2 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA3, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA3 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA3, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA3 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA4, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA4 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA4, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA4 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA5, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA5 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA5, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA5 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA6, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA6 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA6, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA6 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA7, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA7 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA7, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA7 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA8, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA8 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA8, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA8 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA9, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA9 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA9, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA9 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge TA10, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, posedge TA10 &&& check2, DMY_SPC, notifier_rt);
        $setup(negedge TA10, posedge TBE &&& check2, DMY_SPC, notifier_rt);
        $hold(posedge TBE, negedge TA10 &&& check2, DMY_SPC, notifier_rt);
        $setup(posedge CSB, posedge BE &&& check3, DMY_SPC, notifier_r);
        $hold(posedge BE, posedge CSB &&& check3, DMY_SPC, notifier_r);
        $setup(negedge CSB, posedge BE &&& check3, DMY_SPC, notifier_r);
        $hold(posedge BE, negedge CSB &&& check3, DMY_SPC, notifier_r);

        $setup(posedge TEST, posedge TBE &&& check4, DMY_SPC, notifier_rt);
        $hold(posedge TBE &&& check4, posedge TEST, DMY_SPC, notifier_rt);
        $setup(negedge TEST, posedge TBE &&& check4, DMY_SPC );
        $hold(posedge TBE &&& check4, negedge TEST, DMY_SPC );
        $setup(posedge TEST, negedge TBE &&& check4, DMY_SPC );
        $hold(negedge TBE &&& check4, posedge TEST, DMY_SPC );
        $setup(negedge TEST, negedge TBE &&& check4, DMY_SPC );
        $hold(negedge TBE &&& check4, negedge TEST, DMY_SPC );
        $setup(posedge BUNRI, posedge BE &&& check6, DMY_SPC );
        $hold(posedge BE &&& check6, posedge BUNRI, DMY_SPC );
        $setup(negedge BUNRI, posedge BE &&& check6, DMY_SPC, notifier_r);
        $hold(posedge BE &&& check6, negedge BUNRI, DMY_SPC, notifier_r);
        $setup(posedge BUNRI, negedge BE &&& check6, DMY_SPC );
        $hold(negedge BE &&& check6, posedge BUNRI, DMY_SPC );
        $setup(negedge BUNRI, negedge BE &&& check6, DMY_SPC );
        $hold(negedge BE &&& check6, negedge BUNRI, DMY_SPC );
        $setup(posedge BUNRI, posedge TBE &&& check5, DMY_SPC, notifier_rt);
        $hold(posedge TBE &&& check5, posedge BUNRI, DMY_SPC, notifier_rt);
        $setup(negedge BUNRI, posedge TBE &&& check5, DMY_SPC );
        $hold(posedge TBE &&& check5, negedge BUNRI, DMY_SPC );
        $setup(posedge BUNRI, negedge TBE &&& check5, DMY_SPC );
        $hold(negedge TBE &&& check5, posedge BUNRI, DMY_SPC );
        $setup(negedge BUNRI, negedge TBE &&& check5, DMY_SPC );
        $hold(negedge TBE &&& check5, negedge BUNRI, DMY_SPC );

        $width(posedge BE &&& check1, DMY_SPC, 0, notifier_r);
        $width(negedge BE &&& check1, DMY_SPC, 0, notifier_r);
        $width(posedge TBE &&& check2, DMY_SPC, 0, notifier_rt);
        $width(negedge TBE &&& check2, DMY_SPC, 0, notifier_rt);

        $period(posedge BE &&& check3, DMY_SPC, notifier_rp);
        $period(posedge TBE &&& check2, DMY_SPC, notifier_rt);

        (BE=>DO0)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO1)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO2)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO3)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO4)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO5)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO6)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO7)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO8)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO9)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO10)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO11)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO12)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO13)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO14)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (BE=>DO15)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO0)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO1)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO2)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO3)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO4)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO5)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO6)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO7)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO8)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO9)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO10)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO11)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO12)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO13)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO14)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);
        (TBE=>TDO15)=(DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC);

        (BUNRI=>DO0)=1;
        (BUNRI=>DO1)=1;
        (BUNRI=>DO2)=1;
        (BUNRI=>DO3)=1;
        (BUNRI=>DO4)=1;
        (BUNRI=>DO5)=1;
        (BUNRI=>DO6)=1;
        (BUNRI=>DO7)=1;
        (BUNRI=>DO8)=1;
        (BUNRI=>DO9)=1;
        (BUNRI=>DO10)=1;
        (BUNRI=>DO11)=1;
        (BUNRI=>DO12)=1;
        (BUNRI=>DO13)=1;
        (BUNRI=>DO14)=1;
        (BUNRI=>DO15)=1;
        (BUNRI=>TDO0)=1;
        (BUNRI=>TDO1)=1;
        (BUNRI=>TDO2)=1;
        (BUNRI=>TDO3)=1;
        (BUNRI=>TDO4)=1;
        (BUNRI=>TDO5)=1;
        (BUNRI=>TDO6)=1;
        (BUNRI=>TDO7)=1;
        (BUNRI=>TDO8)=1;
        (BUNRI=>TDO9)=1;
        (BUNRI=>TDO10)=1;
        (BUNRI=>TDO11)=1;
        (BUNRI=>TDO12)=1;
        (BUNRI=>TDO13)=1;
        (BUNRI=>TDO14)=1;
        (BUNRI=>TDO15)=1;
        (TEST=>TDO0)=1;
        (TEST=>TDO1)=1;
        (TEST=>TDO2)=1;
        (TEST=>TDO3)=1;
        (TEST=>TDO4)=1;
        (TEST=>TDO5)=1;
        (TEST=>TDO6)=1;
        (TEST=>TDO7)=1;
        (TEST=>TDO8)=1;
        (TEST=>TDO9)=1;
        (TEST=>TDO10)=1;
        (TEST=>TDO11)=1;
        (TEST=>TDO12)=1;
        (TEST=>TDO13)=1;
        (TEST=>TDO14)=1;
        (TEST=>TDO15)=1;
    endspecify
`endif // NEC_RTL_SIM

`ifdef NEC_RTL_SIM
task PrintRTLMsg;
    begin
        $display("=======================================================");
        $display("Pure Behavior Function Mode : WBROMSMHS2048W16C5N01");
        $display("Instance      : %m");
        $display("Abstract Delay :");
        $display("  tACC          : %d",tACC);
        $display("=======================================================");
    end
endtask
`endif // NEC_RTL_SIM

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine