// VERSION:1.00 DATE:01/02/06 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif

module TBGTSMLALADCLX4 ( N01, H01, H02, H03 );

    input H01;
    input H02;
    input H03;
    output N01;

    reg notifier;

    // Dummy Buffer
    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H03, H03 );

    or ( _G001, _H03, _H01 );
    not ( _H02B, _H02 );
    DLSFQ ( _enl, _G001, _H02B, 1'b1, 1'b1, notifier );
    and ( N01, _enl, _H02 );

    specify
        specparam DMY_SPC=10;

        $setup ( posedge H01, posedge H02, DMY_SPC, notifier );
        $setup ( negedge H01, posedge H02, DMY_SPC, notifier );
        $hold ( posedge H02, posedge H01, DMY_SPC, notifier );
        $hold ( posedge H02, negedge H01, DMY_SPC, notifier );
        $setup ( posedge H03, posedge H02, DMY_SPC, notifier );
        $setup ( negedge H03, posedge H02, DMY_SPC, notifier );
        $hold ( posedge H02, posedge H03, DMY_SPC, notifier );
        $hold ( posedge H02, negedge H03, DMY_SPC, notifier );

        $width ( negedge H02, DMY_SPC, 0, notifier );

        ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
    endspecify

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine