TDBIAUSBNNLPOC.v
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// VERSION:1.00 DATE:2002/07/26 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIAUSBNNLPOC ( N01, N02, N03, N04, N05, H01, H02, H03, H04, H05, H06, H07, H08 );
inout N01;
output N02;
output N03;
output N04;
output N05;
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
input H07;
input H08;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
buf ( _H07, H07 );
buf ( _H08, H08 );
nor ( _G002, _H01, _H03 );
and ( _ENA, _H02, _H08 );
bufif1 ( _G003, _ENA, _H04 );
buf ( _G004, _G003 );
bufif1 ( _G005, _G002, _G004 );
bufif1 ( N01, _G005, _G004 );
TDBIAUSBNNLPOC_PECL u1 ( _G006, _H05, N01 );
and ( _G014, _G006, _H06 );
bufif1 ( _G007, _G014, _H04 );
buf ( N02, _G007 );
nor ( _G008, N01, _H05, _H07 );
bufif1 ( _G009, _G008, _H04 );
buf ( N03, _G009 );
or ( _G010, N01, _H07 );
bufif1 ( _G011, _G010, _H04 );
buf ( N04, _G011 );
or ( _G012, _H05, _H07 );
bufif1 ( _G013, _G012, _H04 );
buf ( N05, _G013 );
defparam u1.PECL_DLY = 40001;
wire flag_PECL = u1.flag_PECL;
specify
specparam DMY_SPC=1:1:1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !flag_PECL )
( H05 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N03 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N05 ) = ( DMY_SPC, DMY_SPC );
( H06 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H07 *> N03 ) = ( DMY_SPC, DMY_SPC );
( H07 *> N04 ) = ( DMY_SPC, DMY_SPC );
( H07 *> N05 ) = ( DMY_SPC, DMY_SPC );
( H08 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
if ( !flag_PECL )
( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N03 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N04 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine