// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDIPAC33DKS ( N01, H01 );
    output N01;
    input H01;

    pmos ( _H01, H01, 1'b0 );
    buf ( N01, _H01 );
    nmos ( _H01, _H01_int, _G001 );
    pulldown ( _H01_int );
    not #1( _G001, N01 );

    specify
        specparam DMY_SPC=1;

    	( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine