// VERSION:1.00 DATE:2001/10/12 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDIPAST3R ( H01 );
    input H01;

    buf ( _H01, H01 );

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine