TDVSAUSBN.v
473 Bytes
// VERSION:1.00 DATE:2002/07/26 OPENCAD Verilog LIBRARY (1ps)
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDVSAUSBN ( N01, H01 );
input H01;
output N01;
buf ( _H01, H01 );
buf ( N01, _H01 );
specify
specparam DMY_SPC=1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine