TDSECCGX4.v
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// VERSION:1.00 DATE:00/09/20 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSECCGX4 ( N01, N02, N03, H01, H02 );
input H01;
input H02;
output N01;
output N02;
output N03;
reg notif_sc, notif_sc2, notif;
buf ( _H01, H01 );
buf ( _H02, H02 );
not ( _H01N, _H01 );
DESFQB ( _G001, _N01, _H01N, _H02, 1'b1, notif_sc );
buf #1 ( _N01, _G001 );
DESFQB ( _G002, _N02, _H01, _H02, 1'b1, notif_sc2 );
buf #1 ( _N02, _G002 );
not ( N01, _G001 );
not ( N02, _G002 );
buf ( N03, _G002 );
initial begin
notif_sc = 0;
notif_sc2 = 0;
notif = 0;
end
always @ ( notif ) begin
notif_sc = ~notif_sc;
notif_sc2 = ~notif_sc2;
end
specify
specparam DMY_SPC=1;
$setup ( posedge H02, negedge H01, DMY_SPC, notif_sc );
$hold ( negedge H01, posedge H02, DMY_SPC, notif_sc );
$setup ( posedge H02, posedge H01, DMY_SPC, notif_sc2 );
$hold ( posedge H01, posedge H02, DMY_SPC, notif_sc2 );
$width ( negedge H02, DMY_SPC, 0, notif );
( H01 => N01 ) = ( DMY_SPC, DMY_SPC );
( H01 => N02 ) = ( DMY_SPC, DMY_SPC );
( H01 => N03 ) = ( DMY_SPC, DMY_SPC );
( H02 => N01 ) = ( DMY_SPC, DMY_SPC );
( H02 => N02 ) = ( DMY_SPC, DMY_SPC );
( H02 => N03 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine