// VERSION:1.00 DATE:2001/09/25 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDOSAC33N40M ( N01, N02, H01, H02 );
    output N01;
    output N02;
    input H01;
    input H02;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    not ( _G001, _H02 );
    bufif1 ( _H01, _H02, _G001 );
    not ( _G002, _H01 );
    buf ( N02, _G002 );
    not ( _G003, _G002 );
    and ( N01, _G003, _H02 );

    specify
        specparam DMY_SPC=1;

        ( H01 +*> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H01 -*> N02 ) = ( DMY_SPC, DMY_SPC );
        ( H02 +*> N01 ) = ( 1:1:1, DMY_SPC );
        ( H02 -*> N02 ) = ( 1:1:1, 1:1:1 );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine