TBAN222X1.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBAN222X1 ( N01, H01, H02, H03, H04, H05, H06 );
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
output N01;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
and ( _G001, _H01, _H02 );
and ( _G002, _H03, _H04 );
and ( _G003, _H05, _H06 );
nor ( N01, _G001, _G002, _G003 );
specify
specparam DMY_SPC=1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H04 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H06 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine