// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TBNR4X2 ( N01, H01, H02, H03, H04 );
    input H01;
    input H02;
    input H03;
    input H04;
    output N01;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H03, H03 );
    buf ( _H04, H04 );
    nor ( N01, _H01, _H02, _H03, _H04 );

    specify
        specparam DMY_SPC=1;

        ( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
        ( H04 *> N01 ) = ( DMY_SPC, DMY_SPC );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine