TDMXB2X1.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDMXB2X1 ( N01 , H01 , H02 , H03 , H04 , H05 ) ;
input H01 ;
input H02 ;
input H03 ;
input H04 ;
input H05 ;
output N01 ;
buf ( _H01 , H01 ) ;
buf ( _H02 , H02 ) ;
buf ( _H03 , H03 ) ;
buf ( _H04 , H04 ) ;
buf ( _H05 , H05 ) ;
and ( C2 , _H03 , _H02 ) ;
not ( C4 , _H03 ) ;
and ( C3 , C4 , _H01 ) ;
and ( C5 , _H01 , _H02 ) ;
or ( M0 , C2 , C3 , C5 ) ;
not ( C8 , M0 ) ;
not ( C9 , _H04 ) ;
and ( C7 , C8 , C9 ) ;
not ( C11 , _H05 ) ;
and ( C10 , M0 , C11 ) ;
not ( C13 , _H04 ) ;
not ( C14 , _H05 ) ;
and ( C12 , C13 , C14 ) ;
or ( N01 , C7 , C10 , C12 ) ;
specify
specparam DMY_SPC=1;
( H04 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H01 )
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H01 )
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine