// VERSION:4.01 DATE:2000/11/08 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TBCLHOLD ( N01 );
    inout N01;

    not (NET1, N01);
    not (pull1, pull0) #1 (N01, 1'bx);

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine