// test.v v1 Frank Berndt
// r4300 code test;
// :set tabstop=4

`timescale 1ps/1ps

`define	TCO #0

module test;

	// instantiate the cpu model;

	// clock/reset generation;

	reg sysclk;				// system clock;
	reg [2:0] divmode;		// cpu frequency mode;
	reg coldrst_l;			// cpu cold reset;
	reg warmrst_l;			// cpu wam reset;
	wire pll_lock;

	// dump control;

	initial
		$dumpvars;

	// clock generator;

	initial
		sysclk = 0;
	always
		#6000 sysclk = ~sysclk;

	// reset logic;

	initial
	begin
		divmode = 3'b000;
		coldrst_l = 1;
		warmrst_l = 1;
		repeat(4) @(posedge sysclk);
		`TCO;
		coldrst_l = 0;
		warmrst_l = 0;
		repeat(4) @(posedge sysclk);
		`TCO;
		coldrst_l = 1;
		repeat(16) @(posedge sysclk);
		`TCO;
		warmrst_l = 1;
	end

	wire `TCO eok_l;			// external agent ok;
	wire [31:0] sysad_out;		// system addr/data from cpu;
	wire [4:0] syscmd_out;		// system command from cpu;
	wire pvalid_l;				// processor data valid;
	wire [31:0] `TCO sysad_in;	// system addr/data to cpu;
	wire [4:0] `TCO syscmd_in;	// system command to cpu;
	wire `TCO evalid_l;			// external data valid;
	wire [4:0] `TCO int_l;		// cpu interrupts;
	wire `TCO nmi_l;			// non-maskable interrupt;

	// do not use interrupts or nmi;

	assign int_l = 5'b11111;
	assign nmi_l = 1'b1;

	// instantiate NEC cpu model;

	NB4300V01 cpu (
		.MASTERCLOCK(sysclk),
		.ISYSCMD4(syscmd_in[4]),
		.ISYSCMD3(syscmd_in[3]),
		.ISYSCMD2(syscmd_in[2]),
		.ISYSCMD1(syscmd_in[1]),
		.ISYSCMD0(syscmd_in[0]),
		.OSYSCMD4(syscmd_out[4]),
		.OSYSCMD3(syscmd_out[3]),
		.OSYSCMD2(syscmd_out[2]),
		.OSYSCMD1(syscmd_out[1]),
		.OSYSCMD0(syscmd_out[0]),
		.ISYSAD31(sysad_in[31]),
		.ISYSAD30(sysad_in[30]),
		.ISYSAD29(sysad_in[29]),
		.ISYSAD28(sysad_in[28]),
		.ISYSAD27(sysad_in[27]),
		.ISYSAD26(sysad_in[26]),
		.ISYSAD25(sysad_in[25]),
		.ISYSAD24(sysad_in[24]),
		.ISYSAD23(sysad_in[23]),
		.ISYSAD22(sysad_in[22]),
		.ISYSAD21(sysad_in[21]),
		.ISYSAD20(sysad_in[20]),
		.ISYSAD19(sysad_in[19]),
		.ISYSAD18(sysad_in[18]),
		.ISYSAD17(sysad_in[17]),
		.ISYSAD16(sysad_in[16]),
		.ISYSAD15(sysad_in[15]),
		.ISYSAD14(sysad_in[14]),
		.ISYSAD13(sysad_in[13]),
		.ISYSAD12(sysad_in[12]),
		.ISYSAD11(sysad_in[11]),
		.ISYSAD10(sysad_in[10]),
		.ISYSAD9(sysad_in[9]),
		.ISYSAD8(sysad_in[8]),
		.ISYSAD7(sysad_in[7]),
		.ISYSAD6(sysad_in[6]),
		.ISYSAD5(sysad_in[5]),
		.ISYSAD4(sysad_in[4]),
		.ISYSAD3(sysad_in[3]),
		.ISYSAD2(sysad_in[2]),
		.ISYSAD1(sysad_in[1]),
		.ISYSAD0(sysad_in[0]),
		.OSYSAD31(sysad_out[31]),
		.OSYSAD30(sysad_out[30]),
		.OSYSAD29(sysad_out[29]),
		.OSYSAD28(sysad_out[28]),
		.OSYSAD27(sysad_out[27]),
		.OSYSAD26(sysad_out[26]),
		.OSYSAD25(sysad_out[25]),
		.OSYSAD24(sysad_out[24]),
		.OSYSAD23(sysad_out[23]),
		.OSYSAD22(sysad_out[22]),
		.OSYSAD21(sysad_out[21]),
		.OSYSAD20(sysad_out[20]),
		.OSYSAD19(sysad_out[19]),
		.OSYSAD18(sysad_out[18]),
		.OSYSAD17(sysad_out[17]),
		.OSYSAD16(sysad_out[16]),
		.OSYSAD15(sysad_out[15]),
		.OSYSAD14(sysad_out[14]),
		.OSYSAD13(sysad_out[13]),
		.OSYSAD12(sysad_out[12]),
		.OSYSAD11(sysad_out[11]),
		.OSYSAD10(sysad_out[10]),
		.OSYSAD9(sysad_out[9]),
		.OSYSAD8(sysad_out[8]),
		.OSYSAD7(sysad_out[7]),
		.OSYSAD6(sysad_out[6]),
		.OSYSAD5(sysad_out[5]),
		.OSYSAD4(sysad_out[4]),
		.OSYSAD3(sysad_out[3]),
		.OSYSAD2(sysad_out[2]),
		.OSYSAD1(sysad_out[1]),
		.OSYSAD0(sysad_out[0]),
		.SYSEN(),				// XXX
		.PVALIDB(pvalid_l),
		.PREQB(),				// unused;
		.PMASTERB(),			// unused;
		.NMIB(nmi_l),
		.INTB4(int_l[4]),
		.INTB3(int_l[3]),
		.INTB2(int_l[2]),
		.INTB1(int_l[1]),
		.INTB0(int_l[0]),
		.EVALIDB(evalid_l),
		.EREQB(1'b1),			// never requested;
		.EOKB(eok_l),
		.DIVMODE2(divmode[2]),
		.DIVMODE1(divmode[1]),
		.DIVMODE0(divmode[0]),
		.COLDRESETB(coldrst_l),
		.RESETB(warmrst_l),
		.PLOCK(pll_lock),
		.SI7(1'b0),				// XXX
		.SI6(1'b0),				// XXX
		.SI5(1'b0),				// XXX
		.SI4(1'b0),				// XXX
		.SI3(1'b0),				// XXX
		.SI2(1'b0),				// XXX
		.SI1(1'b0),				// XXX
		.SI0(1'b0),				// XXX
		.SO7(),					// XXX
		.SO6(),					// XXX
		.SO5(),					// XXX
		.SO4(),					// XXX
		.SO3(),					// XXX
		.SO2(),					// XXX
		.SO1(),					// XXX
		.SO0(),					// XXX
		.BUNRI(1'b0),			// XXX normal mode;
		.TBI51(1'b0),			// XXX test bus input;
		.TBI50(1'b0),			// XXX test bus input;
		.TBI49(1'b0),			// XXX test bus input;
		.TBI48(1'b0),			// XXX test bus input;
		.TBI47(1'b0),			// XXX test bus input;
		.TBI46(1'b0),			// XXX test bus input;
		.TBI45(1'b0),			// XXX test bus input;
		.TBI44(1'b0),			// XXX test bus input;
		.TBI43(1'b0),			// XXX test bus input;
		.TBI42(1'b0),			// XXX test bus input;
		.TBI41(1'b0),			// XXX test bus input;
		.TBI40(1'b0),			// XXX test bus input;
		.TBI39(1'b0),			// XXX test bus input;
		.TBI38(1'b0),			// XXX test bus input;
		.TBI37(1'b0),			// XXX test bus input;
		.TBI36(1'b0),			// XXX test bus input;
		.TBI35(1'b0),			// XXX test bus input;
		.TBI34(1'b0),			// XXX test bus input;
		.TBI33(1'b0),			// XXX test bus input;
		.TBI32(1'b0),			// XXX test bus input;
		.TBI31(1'b0),			// XXX test bus input;
		.TBI30(1'b0),			// XXX test bus input;
		.TBI29(1'b0),			// XXX test bus input;
		.TBI28(1'b0),			// XXX test bus input;
		.TBI27(1'b0),			// XXX test bus input;
		.TBI26(1'b0),			// XXX test bus input;
		.TBI25(1'b0),			// XXX test bus input;
		.TBI24(1'b0),			// XXX test bus input;
		.TBI23(1'b0),			// XXX test bus input;
		.TBI22(1'b0),			// XXX test bus input;
		.TBI21(1'b0),			// XXX test bus input;
		.TBI20(1'b0),			// XXX test bus input;
		.TBI19(1'b0),			// XXX test bus input;
		.TBI18(1'b0),			// XXX test bus input;
		.TBI17(1'b0),			// XXX test bus input;
		.TBI16(1'b0),			// XXX test bus input;
		.TBI15(1'b0),			// XXX test bus input;
		.TBI14(1'b0),			// XXX test bus input;
		.TBI13(1'b0),			// XXX test bus input;
		.TBI12(1'b0),			// XXX test bus input;
		.TBI11(1'b0),			// XXX test bus input;
		.TBI10(1'b0),			// XXX test bus input;
		.TBI9(1'b0),			// XXX test bus input;
		.TBI8(1'b0),			// XXX test bus input;
		.TBI7(1'b0),			// XXX test bus input;
		.TBI6(1'b0),			// XXX test bus input;
		.TBI5(1'b0),			// XXX test bus input;
		.TBI4(1'b0),			// XXX test bus input;
		.TBI3(1'b0),			// XXX test bus input;
		.TBI2(1'b0),			// XXX test bus input;
		.TBI1(1'b0),			// XXX test bus input;
		.TBI0(1'b0),			// XXX test bus input;
		.TBO39(),				// XXX test bus output;
		.TBO38(),				// XXX test bus output;
		.TBO37(),				// XXX test bus output;
		.TBO36(),				// XXX test bus output;
		.TBO35(),				// XXX test bus output;
		.TBO34(),				// XXX test bus output;
		.TBO33(),				// XXX test bus output;
		.TBO32(),				// XXX test bus output;
		.TBO31(),				// XXX test bus output;
		.TBO30(),				// XXX test bus output;
		.TBO29(),				// XXX test bus output;
		.TBO28(),				// XXX test bus output;
		.TBO27(),				// XXX test bus output;
		.TBO26(),				// XXX test bus output;
		.TBO25(),				// XXX test bus output;
		.TBO24(),				// XXX test bus output;
		.TBO23(),				// XXX test bus output;
		.TBO22(),				// XXX test bus output;
		.TBO21(),				// XXX test bus output;
		.TBO20(),				// XXX test bus output;
		.TBO19(),				// XXX test bus output;
		.TBO18(),				// XXX test bus output;
		.TBO17(),				// XXX test bus output;
		.TBO16(),				// XXX test bus output;
		.TBO15(),				// XXX test bus output;
		.TBO14(),				// XXX test bus output;
		.TBO13(),				// XXX test bus output;
		.TBO12(),				// XXX test bus output;
		.TBO11(),				// XXX test bus output;
		.TBO10(),				// XXX test bus output;
		.TBO9(),				// XXX test bus output;
		.TBO8(),				// XXX test bus output;
		.TBO7(),				// XXX test bus output;
		.TBO6(),				// XXX test bus output;
		.TBO5(),				// XXX test bus output;
		.TBO4(),				// XXX test bus output;
		.TBO3(),				// XXX test bus output;
		.TBO2(),				// XXX test bus output;
		.TBO1(),				// XXX test bus output;
		.TBO0(),				// XXX test bus output;
		.TEST(1'b0),			// XXX test mode;
		.TEST1(1'b0),			// XXX test mode;
		.TEST0(1'b0),			// XXX test mode;
		.SCANSMC(1'b0),
		.SCANTMC(1'b0),
		.BYPASSPLLMODE(1'b0),
		.BYPASSPLLPCLK(1'b0),
		.BYPASSPLLSCLK(1'b0),
		.AVDD1(1'b1),
		.AGND1(1'b0)
	);

	// short-cut cpu pll timing;

	always @(cpu.NB4300.pll.ABPLSSCH_IF.PLL._STBY)
	begin
		if(cpu.NB4300.pll.ABPLSSCH_IF.PLL._STBY == 1)
			force cpu.NB4300.pll.ABPLSSCH_IF.PLL._PBSTBY = 1'b1;
		if(cpu.NB4300.pll.ABPLSSCH_IF.PLL._STBY == 0)
			force cpu.NB4300.pll.ABPLSSCH_IF.PLL._PBSTBY = 1'b0;
	end

	// instantiate cpu monitor;

	cpu_mon cpu_mon (
		.sysclk(sysclk),
		.divmode(divmode),
		.coldrst_l(coldrst_l),
		.warmrst_l(warmrst_l),
		.eok_l(eok_l),
		.sysad_out(sysad_out),
		.syscmd_out(syscmd_out),
		.pvalid_l(pvalid_l),
		.sysad_in(sysad_in),
		.syscmd_in(syscmd_in),
		.evalid_l(evalid_l),
		.int_l(int_l),
		.nmi_l(nmi_l),
		.secure(1'b0)
	);

	// internal memories;

	reg [31:0] brom [0:4*1024-1];
	reg [31:0] bram [0:16*1024-1];
	reg [31:0] iram [0:8*1024-1];

	initial
		$readmemh("rom.sim", brom);

	// read word;
	// all other spaces return 0;

	task rword;
		input [31:0] addr;		// byte address;
		input [2:0] sbo;		// sub-block order;
		output [31:0] word;		// word read;
		reg [13:0] wa;			// word address;
		begin
			wa[13:3] = addr[15:5];
			wa[2:0] = addr[4:2] ^ sbo;
			case(addr[31:16])
				16'h1fc0: word = brom[wa];
				16'h1fc2: word = bram[wa];
				16'h1fc4: word = iram[wa];
				default: word = 32'd0;
			endcase
		end
	endtask

	// write word;
	// all other spaces are dropped;

	task wword;
		input [31:0] addr;		// byte address;
		input [2:0] sbo;		// sub-block order;
		input [31:0] word;		// write data;
		input [31:0] mask;		// write mask;
		reg [13:0] wa;			// word address;
		begin
			wa[13:3] = addr[15:5];
			wa[2:0] = addr[4:2] ^ sbo;
			case(addr[31:16])
				16'h1fc0: brom[wa] = (brom[wa] & ~mask) | (word & mask);
				16'h1fc2: bram[wa] = (bram[wa] & ~mask) | (word & mask);
				16'h1fc4: iram[wa] = (iram[wa] & ~mask) | (word & mask);
			endcase
		end
	endtask

	// requests state machine;

	wire reset_l;
	reg sys_ack;
	wire cmd_iss;
	reg sys_eok_l;
	reg sys_iss; 
	reg sys_busy;

	assign reset_l = coldrst_l & warmrst_l;
	assign cmd_iss = sys_iss & ~pvalid_l & ~syscmd_out[4];

	always @(posedge sysclk)
	begin
		if(reset_l)
			sys_ack <= 0;
		sys_eok_l <= ~reset_l | cmd_iss | (sys_busy & ~sys_ack);
		sys_iss <= reset_l & ~sys_eok_l;
		sys_busy <= reset_l & ~sys_ack & (sys_busy | cmd_iss);
	end

	assign eok_l = sys_eok_l;

	// hold on to address/cmd;

	reg [31:0] sys_addr;
	reg [4:0] sys_cmd;
	integer sys_nwr;

	always @(posedge sysclk)
	begin
		if(cmd_iss) begin
			sys_addr <= sysad_out;
			sys_cmd <= syscmd_out;
			sys_nwr <= 0;
		end
	end

	// write state machine;

	reg [31:0] mask;
	integer nwr;

	always @(sys_cmd or sys_addr)
	begin
		nwr = 0;
		case(sys_cmd[2:0])
			3'b000,				// 1-byte write;
			3'b001,				// 2-byte write;
			3'b010,				// 3-byte write;
			3'b011: nwr = 1;	// 4-byte write;
			3'b100: nwr = 2;	// 8-byte write;
			3'b101: nwr = 4;	// 16-byte write;
			3'b110: nwr = 8;	// 32-byte write;
		endcase
		mask = 32'd0;
		case({sys_cmd[2:0], sys_addr[1:0]})
			{ 3'b000, 2'b00 }: mask = 32'hff000000;
			{ 3'b000, 2'b01 }: mask = 32'h00ff0000;
			{ 3'b000, 2'b10 }: mask = 32'h0000ff00;
			{ 3'b000, 2'b11 }: mask = 32'h000000ff;
			{ 3'b001, 2'b00 }: mask = 32'hffff0000;
			{ 3'b001, 2'b10 }: mask = 32'h0000ffff;
			{ 3'b010, 2'b00 }: mask = 32'hffffff00;
			{ 3'b010, 2'b01 }: mask = 32'h00ffffff;
			{ 3'b011, 2'b00 }: mask = 32'hffffffff;
		endcase
		@(posedge sysclk);
		@(posedge sysclk);
		sys_ack = 1;
		@(posedge sysclk);
		sys_ack = 0;
	end

	wire write;

	assign write = syscmd_out[4] & ~pvalid_l;

	always @(posedge sysclk)
	begin
		if(sys_cmd[3] & write & (sys_nwr < nwr)) begin
			wword(sys_addr, sys_nwr, sysad_out, mask);
			sys_nwr = sys_nwr + 1;
		end
	end

	// read response state machine;

	integer nrsp, nr;
	reg [31:0] sysad_rsp;
	reg [4:0] syscmd_rsp;
	reg sys_evalid_l;

	always @(negedge reset_l)
		sys_evalid_l = 1;

	always @(posedge sys_busy)
	begin
		@(posedge sysclk);
		if(sys_cmd[3] === 1'b0) begin
			nrsp = 0;
			case(sys_cmd[2:0])
				3'b000,				// 1-byte read;
				3'b001,				// 2-byte read;
				3'b010,				// 3-byte read;
				3'b011: nrsp = 1;	// 4-byte read;
				3'b100: nrsp = 2;	// 8-byte read;
				3'b101: nrsp = 4;	// 16-byte read;
				3'b110: nrsp = 8;	// 32-byte read;
			endcase
			for(nr = 0; nr < nrsp; nr = nr + 1) begin
				rword(sys_addr, nr, sysad_rsp);
				syscmd_rsp[4] = 1;
				syscmd_rsp[3] = ((nr + 1) != nrsp);
				syscmd_rsp[2] = 0;
				syscmd_rsp[1] = 0;
				syscmd_rsp[0] = 0;
				sys_evalid_l = 0;
				@(posedge sysclk);
			end
			sys_evalid_l = 1;
		end
	end

	assign sysad_in = sysad_rsp;
	assign syscmd_in = syscmd_rsp;
	assign evalid_l = sys_evalid_l;

endmodule