////////////////////////////////////////////////////////////////////////////////
// TC58512FT 512Mbit(x8) NAND Flash Memory Verilog Simulation Model           //
// Version: 1.2                                                               //
// Date: 2001/07/18                                                           //
// Programmed By Y.Motizuki at FLASH MEMORY TECHNICAL MARKETING GROUP         //
// module : TC58512FT                                                         //
//                                                                            //
//   Copyright (c) 2001 TOSHIBA CORPORATION, All Rights Reserved.             //
////////////////////////////////////////////////////////////////////////////////
// Revision History                 Description                               //
//                         : 1.1   2001/06/10 1st Release                     //
//                         : 1.2   2001/07/18 Timing Check modify             //
////////////////////////////////////////////////////////////////////////////////
`timescale      1ns/1ns

//------------------------------------------------------------------------------
// Memory Initialize Option
//------------------------------------------------------------------------------
// If This value is defined "1", whole CHIP data "1" except for Bad Block.
// It is better to define "0" to speed up simulation.
//------------------------------------------------------------------------------

`define MemoryInitEnable     0    // Not Memory Initialize (recommended)

//------------------------------------------------------------------------------
//  Difinitions Size of Memory
//------------------------------------------------------------------------------
//  "blk_bit" is width of bits for block address in a chip 1Chip=2048Blocks, 11bits requires
//------------------------------------------------------------------------------
`define blk_bit            (11)    // Width of bits for block address

//------------------------------------------------------------------------------
//  Definition regarding AC Specification
//------------------------------------------------------------------------------
`define tCLS                (0)
`define tCLH               (10)
`define tCS                 (0)
`define tCH                (10)
`define tWP                (25)
`define tALS                (0)
`define tALH               (10)
`define tDS                (20)
`define tDH                (10)
`define tWC                (50)
`define tWH                (15)
`define tWW               (100)
`define tRR                (20)
`define tRP                (35)
`define tRC                (50)
`define tREA               (35)
`define tCEH              (100)
`define tREAID             (35)
`define tOH                (10)
`define tRHZ               (30)
`define tCHZ               (20)
`define tREH               (15)
`define tIR                 (0)
`define tRSTO              (35)
`define tCSTO              (45)
`define tRHW                (0)
`define tWHC               (30)
`define tWHR               (30)
`define tAR1              (100)
`define tCR               (100)
`define tWB               (200)
`define tAR2               (50)
`define tRB               (200)
`define tCRY             (1000)

`ifdef  FLASH_FAST
`define tRST_program    (1200)
`define tRST_erase      (1300)
`define tRST_read       (1100)
`define tR              (1000)
`define tPROG           (5000)    // Typical
`define tDBSY           (500)    // Typical
`define tMBPBSY         (5000)    // Typical
`define tBERASE         (5000)    // Typical
`else
`define tRST_program    (10000)
`define tRST_erase     (500000)
`define tRST_read        (6000)
`define tR              (25000)
`define tPROG          (200000)    // Typical
`define tDBSY            (2000)    // Typical
`define tMBPBSY        (200000)    // Typical
`define tBERASE       (2000000)    // Typical
`endif

/*
`define tRST_program   (10000)
`define tRST_erase     (20000)
`define tRST_read       (6000)
`define tR              (2000)
`define tPROG           (3000)
`define tDBSY           (1000)
`define tMBPBSY        (10000)
`define tBERASE        (10000)
*/

//------------------------------------------------------------------------------
//  tCERY : In case of sequential read, if CE gets 1 with in 30nsec, R/B will not go 0.
//          This 30nsec is defined tCERY.
//------------------------------------------------------------------------------
`define tCERY              (30)    // tCERY

//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//                    TC58512FT Simulation Model
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module TC58256FT (
                    IO,
                    CE,
                    WE,
                    RE,
                    CLE,
                    ALE,
                    WP,
                    RY_BY
                  ) ;

//------------------------------------------------------------------------------
//  Definition Fail Address & Fail bit
//------------------------------------------------------------------------------
//  Format is following;
//  ------------------------------------
//  FAIL_ADD[n] = 27'hxxxxxxx
//  FAIL_BIT[n] = 8'byyyyyyyy
//  ------------------------------------
//  xxxxxxx is address in the memory in hexadecimal number and 27bits are effective.
//  from LSB, 10bit = Column Address
//             5bit = Page   Address
//            12bit = Block  Address
//   yyyyyyyy is fail bit in Fail Address.
//   n is fail Address ID Number. (n<FAIL_NUM)
//
//   For example, in case of Block=7 , Page=8 , Column=3 , bit=2,
//   discription is
//        
//   FAIL_ADD[0] = 27'h003a003
//   FAIL_BIT[0] = 8'b00000100
//
//------------------------------------------------------------------------------
parameter FAIL_NUM = 5 ;                          // The Number of Total Fail Address
parameter ADD_BIT = 27 ;                          // Width of bits for address

reg  [ADD_BIT-1:0]  FAIL_ADD [0:FAIL_NUM-1] ;     // FAIL ADD Register
reg  [7:0]  FAIL_BIT[0:FAIL_NUM-1] ;              // FAIL BIT Register

initial begin
    FAIL_ADD[0] = 27'h0000000 ;
    FAIL_ADD[1] = 27'h0000c00 ;
    FAIL_ADD[2] = 27'h0ff7e0f ;
    FAIL_ADD[3] = 27'h0ffbe0f ;
    FAIL_ADD[4] = 27'h0fffe0f ;
    FAIL_BIT[0] = 8'b00001000 ;
    FAIL_BIT[1] = 8'b00010000 ;
    FAIL_BIT[2] = 8'b00100000 ;
    FAIL_BIT[3] = 8'b01000000 ;
    FAIL_BIT[4] = 8'b10000000 ;
end

//------------------------------------------------------------------------------
//  Parameters regarding memory size
//------------------------------------------------------------------------------
parameter D_WIDTH           = 8                ; // Data Width
parameter COL_IN_PAGE       = 528            ; // Number of columns per 1 page
parameter PAGE_IN_BLOCK     = 32             ; // Number of pages per 1 block
parameter ADD_COL           = 9              ; // Width of bits for colmn address
parameter COL_BIT           = 10             ; // Width of bits for colmn
parameter PAG_BIT           = 5              ; // Width of bits for page address
parameter BLK_BIT           = `blk_bit       ; // Width of bits for block address
parameter CHP_BIT           = BLK_BIT+PAG_BIT+COL_BIT ;
                                               // Width of bits for addressing whole chip
parameter AREA_SIZ_A        = 256            ; // Number of column in AREA-A/page
parameter AREA_SIZ_B        = 256            ; // Number of column in AREA-B/page
parameter AREA_SIZ_C        = 16             ; // Number of column in AREA-C/page
parameter AREA_BIT_A        = 8              ; // Width of bits for address in AREA-A
parameter AREA_BIT_B        = 8              ; // Width of bits for address in AREA-B
parameter AREA_BIT_C        = 4              ; // Width of bits for address in AREA-C
parameter ADD_DIV           = 4              ; // How many cycles address is devided and input
parameter ID_ADD_BIT = 3                     ; // The Number of Total Bad Block
parameter DISTRICT_NUM      = 4              ; // Number of District
parameter DISTRICT_BIT_NUM  = 2              ; // Width of bits for District

//------------------------------------------------------------------------------
//  Difinition regarding input/output signal
//------------------------------------------------------------------------------
inout [7:0] IO ;
input  CE ;
input  WE ;
input  RE ;
input  CLE ;
input  ALE ;
input  WP ;
output RY_BY  ;

//------------------------------------------------------------------------------
// Parameters regarding Command
//------------------------------------------------------------------------------
parameter CMD_SERIAL_DATA_INPUT  = 8'h80 ;
parameter CMD_READ_MODE_1        = 8'h00 ;
parameter CMD_READ_MODE_2        = 8'h01 ;
parameter CMD_READ_MODE_3        = 8'h50 ;
parameter CMD_RESET              = 8'hff ;
parameter CMD_AUTO_PROGRAM_TRUE  = 8'h10 ;
parameter CMD_AUTO_BLOCK_ERASE_1 = 8'h60 ;
parameter CMD_AUTO_BLOCK_ERASE_2 = 8'hd0 ;
parameter CMD_STATUS_READ_1      = 8'h70 ;
parameter CMD_ID_READ_1          = 8'h90 ;

parameter CMD_AUTO_PROGRAM_DUMMY = 8'h11 ;
parameter CMD_AUTO_PROGRAM_MULTI = 8'h15 ;
parameter CMD_STATUS_READ_2      = 8'h71 ;
parameter CMD_ID_READ_2          = 8'h91 ;

//------------------------------------------------------------------------------
// Parameters regarding Others
//------------------------------------------------------------------------------
//  PROGRAM,ERASE,INIT : mem_write parameter used in task
//
//    PROGRAM: indicates memory cells are written by Program
//    ERASE:   indicates memory cells are erased by Erase
//    INIT:    indicates memory cells are initialized by Erase
//    XPROGRAM: Before Program, make memory cells unknown
//    XERASE:   Before Erase, make memory cells unknown
//
//------------------------------------------------------------------------------
parameter  PROGRAM = 0 ;
parameter  ERASE   = 1 ;
parameter  INIT    = 2 ;
parameter XPROGRAM = 3 ;
parameter XERASE   = 4 ;

//------------------------------------------------------------------------------
// Main registers
//------------------------------------------------------------------------------
//
//  MEM   : Core of memory
//          Data Width 8bit, number of words 2^27
//
//          Because of column address 10bit, 1Page=1024words exist,
//          but only 528 words are used.
//
//
//                7 6 5 4 3 2 1 0
//              +-----------------+             ---   ---   ---
//              |                 |    0         |     |     |
//              +-----------------+    :         |     |     |
//              |                 |    :         |     |     |
//              |                 |    :       0 Page  |     |
//              |                 |    :         |     |     |
//              +-----------------+    :         |     |     |
//              |                 |   527        |     |     |
//              +-----------------+    :        ---    |     |
//              |XXXXXXXXXXXXXXXXX|    :         |   0 Block |
//              |XXXXXXXXXXXXXXXXX|    :         |     |     |
//              |XXXXXXXXXXXXXXXXX|    :      Not used |     |
//              +-----------------+    :         |     |     |
//              |XXXXXXXXXXXXXXXXX|  1023        |     |     |
//              +-----------------+             ----   |     |
//                                                     |     |
//                                            1 Page   |     |
//                                              :      |     |
//                                              :      |     |
//                                              :      |     |
//                                           31 Page   |     |
//                                                    ---    |
//                                                   1 Block |
//                                                     :     |
//                                                     :     |
//                                                     :     |
//                                                4095 Block |
//                                                          ---
//
//------------------------------------------------------------------------------

reg  [D_WIDTH-1:0] MEM [0:(1<<CHP_BIT)-1] ;    // Memory-Core

reg  [D_WIDTH-1:0] RCOD  ;                     // Command Register
reg  [ADD_BIT-1:0] RADD  ;                     // Address Register
reg  [ADD_BIT-1:0] RADD0 ;                     // Address Register (District0)
reg  [ADD_BIT-1:0] RADD1 ;                     // Address Register (District1)
reg  [ADD_BIT-1:0] RADD2 ;                     // Address Register (District2)
reg  [ADD_BIT-1:0] RADD3 ;                     // Address Register (District3)
reg  [D_WIDTH-1:0] RSTAT ;                     // Status Register
reg  [COL_BIT-1:0] DPNT  ;                     // Data Register Pointer
reg  [D_WIDTH-1:0] DATA0[0:(1<<COL_BIT)-1] ;   // Data Register (District0)
reg  [D_WIDTH-1:0] DATA1[0:(1<<COL_BIT)-1] ;   // Data Register (District1)
reg  [D_WIDTH-1:0] DATA2[0:(1<<COL_BIT)-1] ;   // Data Register (District2)
reg  [D_WIDTH-1:0] DATA3[0:(1<<COL_BIT)-1] ;   // Data Register (District3)

//------------------------------------------------------------------------------
// Declaration regarding RY_BY output signal(Busy signal)
//------------------------------------------------------------------------------
//
//    Final RY_BY signal is generated by AND calculated with the above signals
//    (except BUSY_by_read_sched)
//
//------------------------------------------------------------------------------
reg  BUSY_by_read ;         // for generating RY_BY signal in Read sequence
reg  BUSY_by_program ;      // for generating RY_BY signal in Program sequence
reg  BUSY_by_erase ;        // for generating RY_BY signal in Erase sequence
reg  BUSY_by_reset ;        // for cancellation RY_BY signal by Reset Command
reg  BUSY_by_ce ;           // for cancellation RY_BY signal by CE=1
reg  BUSY_by_read_sched ;   // for scheduling BUSY_by_read

reg bBUSY_by_read ;
reg bBUSY_by_program ;
reg bBUSY_by_erase ;
reg bBUSY_by_reset ;
reg bBUSY_by_ce ;

//==============================================================================
//  Declaration for variables
//==============================================================================
integer column ;
reg read_flg ;
reg DIN_COMPLETE ;
reg read_ok ;

time rCE, fCE, rWE, fWE ;
time rCLE, fCLE, rALE, fALE, rRE, fRE, rCEorRE, fCEorRE ;
time rfIO, rRY_BY, fRY_BY, rWP, fWP ;

time fWE2, fRE2, rCE_RST ;
time IO_hiz ;

//==============================================================================
//  From here, main functions are described
//==============================================================================

//------------------------------------------------------------------------------
// Generate Power On Signal
//------------------------------------------------------------------------------
reg  Power_on ;
initial begin
                       Power_on = 1'b0 ;
        #10            Power_on = 1'b1 ;
        #10            Power_on = 1'b0 ;
end

//------------------------------------------------------------------------------
// Set ID registers & Reset timing variables
//------------------------------------------------------------------------------
reg  [D_WIDTH-1:0] RID1[0:4] ; // ID Register (1)
reg  [D_WIDTH-1:0] RID2[0:4] ; // ID Register (2)
initial begin
  RID1[0] = 8'h98 ; RID1[1] = 8'h75 ; RID1[2] = 8'hA5 ;
  RID1[3] = 8'hC0 ; RID1[4] = 8'h01 ;
  RID2[0] = 8'h20 ; RID2[1] = 8'h46 ; RID2[2] = 8'h3A ;
  RID2[3] = 8'h00 ; RID2[4] = 8'h00 ;

  rCE   = 0   ; fCE   = 0 ;
  rWE   = 0   ; fWE   = 0 ;
  rCLE  = 0   ; fCLE   = 0 ;
  rALE  = 0   ; fALE   = 0 ;
  rRE   = 0   ; fRE   = 0 ;
  rCEorRE = 0 ; fCEorRE = 0 ;
  rRY_BY  = 0 ; fRY_BY  = 0 ;
  rfIO   = 0  ;
  rWP   = 0 ; fWP   = 0 ;
  read_flg = 1'b0 ;
  DIN_COMPLETE = 1'b0 ;
  read_ok = 1'b0 ;
end
parameter ID_NUM        = 5 ;

//------------------------------------------------------------------------------
//  Named with the rule: for input signals, attach 'i'
//                       for output signals, attach 'o'
//
//  Since regarding Output signal RY_BY, output '0' is Strong and output '1' is
//  Weak, it should be output through buffer.
//------------------------------------------------------------------------------
wire [D_WIDTH-1:0] iIO    ;
wire [D_WIDTH-1:0] oIO    ;
wire               eIO    ;
wire               iCE    ;
wire               iWE    ;
wire               iRE    ;
wire               iCLE   ;
wire               iALE   ;
wire               iWP    ;
wire               oRY_BY ;

assign iIO = IO               & {D_WIDTH{1'b1}} ;
assign       IO = (eIO) ? oIO : {D_WIDTH{1'bz}} ;

assign iCE    =  CE    & 1'b1 ;
assign iWE    =  WE    & 1'b1 ;
assign iRE    =  RE    & 1'b1 ;
assign iCLE   =  CLE   & 1'b1 ;
assign iALE   =  ALE   & 1'b1 ;
assign iWP    =  WP    & 1'b1 ;
buf (strong0,weak1) (RY_BY,oRY_BY) ;

//------------------------------------------------------------------------------
// Back up initial values of input signals
//------------------------------------------------------------------------------
//  Named by addition 'b'.
//------------------------------------------------------------------------------
reg  [D_WIDTH-1:0] bIO  ;
reg                bCE  ;
reg                bWE  ;
reg                bRE  ;
reg                bCLE ;
reg                bALE ;
reg                bWP  ;

always @(iIO)      bIO  <= iIO  ;
always @(iCE)      bCE  <= iCE  ;
always @(iWE)      bWE  <= iWE  ;
always @(iRE)      bRE  <= iRE  ;
always @(iCLE)     bCLE <= iCLE ;
always @(iALE)     bALE <= iALE ;
always @(iWP)      bWP  <= iWP  ;

//------------------------------------------------------------------------------
//  Genarate Reset_on signal
//------------------------------------------------------------------------------
//  Reset_on :  has initial value 0, after issueing Reset Command, gets to 1
//              indicates if Reset Command has been issued or not.
//------------------------------------------------------------------------------
reg  Reset_on ;
always @(posedge Power_on or posedge iWE) begin
    if ( Power_on ) begin
`ifdef TOSHIBA_ORIGINAL
        Reset_on <= 1'b0 ;
`else
        Reset_on <= 1'b1 ;
        RADD <= {ADD_BIT{1'b0}};
        RADD0 <= {ADD_BIT{1'b0}} ;
        RADD1 <= {ADD_BIT{1'b0}} ;
        RADD2 <= {ADD_BIT{1'b0}} ;
        RADD3 <= {ADD_BIT{1'b0}} ;
`endif
    end
    else if ( {iCE,iCLE,iALE,iRE}===4'b0101 ) begin
        if ( iIO == CMD_RESET )
            Reset_on <= 1'b1 ;
    end
end

//------------------------------------------------------------------------------
// Write to Command Register
//------------------------------------------------------------------------------
//
//    In Command Write, write IO[8:1] to Command Register,
//    with checking the command is valid or not by the function cmd_check.
//    Only valid commands are issued into Command Register.
//
//------------------------------------------------------------------------------
always @(posedge iWE)
    if ( {iCE,iCLE,iALE,iRE}===4'b0101 )
         if ( cmd_check(RCOD,iIO) ) begin
            RCOD <= iIO ;
            read_flg = 1'b0 ;
         end

//------------------------------------------------------------------------------
// Generate mode signals by decoding Command Register
//------------------------------------------------------------------------------

wire   MOD_SERIAL_DATA_INPUT  ;
wire   MOD_READ_MODE_1        ;
wire   MOD_READ_MODE_2        ;
wire   MOD_READ_MODE_3        ;
wire   MOD_RESET              ;
wire   MOD_AUTO_PROGRAM_TRUE  ;
wire   MOD_AUTO_PROGRAM_DUMMY ;
wire   MOD_AUTO_PROGRAM_MULTI ;
wire   MOD_AUTO_BLOCK_ERASE_1 ;
wire   MOD_AUTO_BLOCK_ERASE_2 ;
wire   MOD_STATUS_READ_1      ;
wire   MOD_STATUS_READ_2      ;
wire   MOD_ID_READ_1          ;
wire   MOD_ID_READ_2          ;

wire   MOD_READ_MODE          ; // Read mode        (1),(2),(3)
wire   MOD_AUTO_PROGRAM       ; // Auto Program     (Treu),(Dummy),(Multi)
wire   MOD_AUTO_BLOCK_ERASE   ; // Auto Block Erase (1),(2)
wire   MOD_STATUS_READ        ; // Status Read      (1),(2)
wire   MOD_ID_READ            ; // ID Read          (1),(2)

assign MOD_SERIAL_DATA_INPUT  = ( RCOD === CMD_SERIAL_DATA_INPUT  ) ;
assign MOD_READ_MODE_1        = ( RCOD === CMD_READ_MODE_1        ) ||
                                ( RCOD === CMD_RESET              ) ;
assign MOD_READ_MODE_2        = ( RCOD === CMD_READ_MODE_2        ) ;
assign MOD_READ_MODE_3        = ( RCOD === CMD_READ_MODE_3        ) ;
assign MOD_RESET              = ( RCOD === CMD_RESET              ) ;
assign MOD_AUTO_PROGRAM_TRUE  = ( RCOD === CMD_AUTO_PROGRAM_TRUE  ) ;
assign MOD_AUTO_PROGRAM_DUMMY = ( RCOD === CMD_AUTO_PROGRAM_DUMMY ) ;
assign MOD_AUTO_PROGRAM_MULTI = ( RCOD === CMD_AUTO_PROGRAM_MULTI ) ;
assign MOD_AUTO_BLOCK_ERASE_1 = ( RCOD === CMD_AUTO_BLOCK_ERASE_1 ) ;
assign MOD_AUTO_BLOCK_ERASE_2 = ( RCOD === CMD_AUTO_BLOCK_ERASE_2 ) ;
assign MOD_STATUS_READ_1      = ( RCOD === CMD_STATUS_READ_1      ) ;
assign MOD_STATUS_READ_2      = ( RCOD === CMD_STATUS_READ_2      ) ;
assign MOD_ID_READ_1          = ( RCOD === CMD_ID_READ_1          ) ;
assign MOD_ID_READ_2          = ( RCOD === CMD_ID_READ_2          ) ;

assign MOD_READ_MODE          = MOD_READ_MODE_1        |
                                MOD_READ_MODE_2        |
                                MOD_READ_MODE_3        ;

assign MOD_AUTO_PROGRAM       = MOD_AUTO_PROGRAM_TRUE  |
                                MOD_AUTO_PROGRAM_DUMMY |
                                MOD_AUTO_PROGRAM_MULTI ;

assign MOD_AUTO_BLOCK_ERASE   = MOD_AUTO_BLOCK_ERASE_1 |
                                MOD_AUTO_BLOCK_ERASE_2 ;

assign MOD_STATUS_READ        = MOD_STATUS_READ_1      |
                                MOD_STATUS_READ_2      ;

assign MOD_ID_READ            = MOD_ID_READ_1          |
                                MOD_ID_READ_2          ;

//------------------------------------------------------------------------------
// Generate signals which indicate the Area in one Page.
//   Since one Page consists of Area A,B,C, the information which
//   area is selected is needed.
//------------------------------------------------------------------------------
//
//  area_a : is '1' when Area A is selected.
//  area_b : is '1' when Area B is selected.
//  area_c : is '1' when Area C is selected.
//
//  area_[abc] doesn't change in case of Serial Data Input
//  area_a = 1 , area_b = 0 , area_c = 0 in case of Read Mode (1)
//  area_a = 0 , area_b = 1 , area_c = 0 in case of Read Mode (2)
//  area_a = 0 , area_b = 0 , area_c = 1 in case of Read Mode (3)
//  area_a = 1 , area_b = 0 , area_c = 0 in case of Reset
//  area_[abc] doesn't change in case of other commands
//
//------------------------------------------------------------------------------

reg area_a ;
reg area_b ;
reg area_c ;

always @(posedge iWE)
    if ( {iCE,iCLE,iALE,oRY_BY,iRE}===5'b01011 )
        case (iIO)
            CMD_SERIAL_DATA_INPUT : {area_a,area_b,area_c} <= {area_a,area_b,area_c} ;
            CMD_READ_MODE_1       : {area_a,area_b,area_c} <= 3'b100 ;
            CMD_READ_MODE_2       : {area_a,area_b,area_c} <= 3'b010 ;
            CMD_READ_MODE_3       : {area_a,area_b,area_c} <= 3'b001 ;
            CMD_RESET             : {area_a,area_b,area_c} <= 3'b100 ;
            default               : {area_a,area_b,area_c} <= {area_a,area_b,area_c} ;
        endcase

//------------------------------------------------------------------------------
//  district : has 2bit and indicates which District is selected.
//             This signal is equivalent to RADD[15:14]
//------------------------------------------------------------------------------
wire [1:0]        district ;
assign district = RADD[(PAG_BIT+ADD_COL+DISTRICT_BIT_NUM-1):(PAG_BIT+ADD_COL)] ;

//------------------------------------------------------------------------------
// Generate position signal of Address, add_pos
//------------------------------------------------------------------------------
//
//  add_pos : counts the cycles of inputs of address
//
//    This variable has initial value 0, and counts up with address inputs.
//
//      Address input is issued into RADD[ 8:0] in case of add_pos = 0.
//      Address input is issued into RADD[16:9] in case of add_pos = 1.
//      Address input is issued into RADD[24:17] in case of add_pos = 2.
//      Address input is issued into RADD[25] in case of add_pos = 3.
//      Address input is not issued, nor counts up incase of add_pos = 4.
//
//------------------------------------------------------------------------------
integer add_pos ;
always @(posedge iWE or posedge oRY_BY ) begin
    if ( {bWE,iWE,iRE}===3'b011 ) begin
        if ( {iCE,iCLE,iALE,oRY_BY}===4'b0101 )
            if ( (iIO === CMD_AUTO_BLOCK_ERASE_1)&&(iWP===1'b1) ) add_pos <= 1 ;
            else                                                  add_pos <= 0 ;
        else if ( {iCE,iCLE,iALE,oRY_BY}===4'b0011 )
            if ( MOD_SERIAL_DATA_INPUT || MOD_READ_MODE || MOD_AUTO_BLOCK_ERASE_1 )
                add_pos <= (add_pos == ADD_DIV) ? ADD_DIV : add_pos + 1 ;
            else if ( MOD_ID_READ )
                add_pos <= 0 ;
    end
    else begin
        add_pos <= 0 ;
    end
end

//------------------------------------------------------------------------------
// Input address to Address Register
//------------------------------------------------------------------------------
//
//    At address input, write IO[8:1] to Address Register RADD.
//
//    Address Register consists of not only RADD but also RADD0,RADD1,RADD2 and RADD3
//    used in Program/Erase, for each District.
//    RADD0,RADD1,RADD2 and RADD3 are also described here.
//
//  [Operation]
//
//      Note that in Multi Block Program, same page number in blocks belonging
//      to other Distrcts is valid.
//      In case of different page nambers, the last input page is valid.
//      Therefore, RADD?[13:9] must always be input the last page address regardless
//      of the number of Districts.
//
//------------------------------------------------------------------------------

always @(posedge iWE or posedge iRE) begin

    //
    // WE signal rising
    //
    if ( {bWE,iWE,iRE}===3'b011 ) begin
        if ( {iCE,iCLE,iALE,oRY_BY}===4'b0100 ) begin
            RADD <= ( iIO == CMD_RESET ) ? {ADD_BIT{1'b0}} : RADD ;
        end
        else if ( {iCE,iCLE,iALE,oRY_BY}===4'b0101 ) begin
            RADD <= ( iIO == CMD_RESET ) ? {ADD_BIT{1'b0}} : {ADD_BIT{1'bx}} ;
            if ( iIO == CMD_RESET ) begin
                RADD0 <= {ADD_BIT{1'b0}} ;
                RADD1 <= {ADD_BIT{1'b0}} ;
                RADD2 <= {ADD_BIT{1'b0}} ;
                RADD3 <= {ADD_BIT{1'b0}} ;
            end
        end
        else if ( {iCE,iCLE,iALE,oRY_BY}===4'b0011 ) begin
            if ( MOD_SERIAL_DATA_INPUT || MOD_READ_MODE )
                case (add_pos)
                          0 : RADD <= {RADD[25:9],area_b,iIO} ;
                          1 : RADD <= {RADD[25:17],iIO,RADD[8:0]} ;
                          2 : RADD <= {RADD[25],iIO,RADD[16:0]} ;
                          3 : begin
                                    RADD <= {iIO,RADD[24:0]} ;
                                    case (district)
                                        0: RADD0[25:14] <= {iIO,RADD[24:14]} ;
                                        1: RADD1[25:14] <= {iIO,RADD[24:14]} ;
                                        2: RADD2[25:14] <= {iIO,RADD[24:14]} ;
                                        3: RADD3[25:14] <= {iIO,RADD[24:14]} ;
                                    endcase
                                    RADD0[13:9] <= RADD[13:9] ;
                                    RADD1[13:9] <= RADD[13:9] ;
                                    RADD2[13:9] <= RADD[13:9] ;
                                    RADD3[13:9] <= RADD[13:9] ;
                                    case (district)
                                        0: RADD0[8:0] <= {RADD[8:0]} ;
                                        1: RADD1[8:0] <= {RADD[8:0]} ;
                                        2: RADD2[8:0] <= {RADD[8:0]} ;
                                        3: RADD3[8:0] <= {RADD[8:0]} ;
                                    endcase
                              end
                    default : RADD <= RADD ;
                endcase
            else if ( MOD_AUTO_BLOCK_ERASE_1 )
                case (add_pos)
                          1 : RADD <= {RADD[25:17],iIO,{ADD_COL{1'b0}}} ;
                          2 : RADD <= {RADD[25],iIO,RADD[16:0]} ;
                          3 : begin
                                    RADD <= {iIO,RADD[24:0]} ;
                                    case (district)
                                        0: RADD0 <= {iIO,RADD[24:0]} ;
                                        1: RADD1 <= {iIO,RADD[24:0]} ;
                                        2: RADD2 <= {iIO,RADD[24:0]} ;
                                        3: RADD3 <= {iIO,RADD[24:0]} ;
                                    endcase
                              end
                    default : RADD <= RADD ;
                endcase
            else if ( MOD_ID_READ ) begin
                case (add_pos)
                          0 : RADD <= {iIO[2:0]} ;
                    default : RADD <= RADD ;
                endcase
           end 
        end
    end

    //
    // RE signal rising
    //
    if ( {bRE,iRE}===2'b01 ) begin
        if ( {iCE,iCLE,iALE,oRY_BY,iWE}===5'b00011 ) begin
            if ( MOD_READ_MODE ) begin
                if ( (DPNT==COL_IN_PAGE-1) ) begin
                    if ( (RADD>>ADD_COL) < {(BLK_BIT+PAG_BIT){1'b1}} ) begin
//                        RADD <= RADD + (1<<ADD_COL) ;
                    end
                end
            end
            if ( MOD_ID_READ ) begin
                if (RADD < ID_NUM-1 ) RADD <= RADD + 1 ;
           end
        end
    end
end

//------------------------------------------------------------------------------
// Flag indicating selected District(for Program)
//------------------------------------------------------------------------------
// program_stack_flag : register of 4bits(bit0 to bit3)
//                      for Program operation, a bit related to a selected District is '1'.
//
//------------------------------------------------------------------------------
reg [DISTRICT_NUM-1:0] program_stack_flag ;
always @(posedge Power_on or posedge iWE) begin
    if ( Power_on ) begin
        program_stack_flag <= {DISTRICT_NUM{1'b0}} ;
    end
    else if ( {iCE,oRY_BY,iRE}===3'b011 ) begin
        if ( {iCLE,iALE}===2'b10 ) begin
            if ( (iIO !== CMD_SERIAL_DATA_INPUT ) &&
                 (iIO !== CMD_AUTO_PROGRAM_DUMMY) &&
                 (iIO !== CMD_STATUS_READ_1 )     &&
                 (iIO !== CMD_STATUS_READ_2 )        ) begin
                program_stack_flag <= {DISTRICT_NUM{1'b0}} ;
            end
        end
        else if ( {iCLE,iALE}===2'b01 ) begin
            if ( MOD_SERIAL_DATA_INPUT ) begin
                if ( add_pos == 1 ) begin
                        program_stack_flag[iIO[6:5]] <= 1'b1 ;
                end
            end
        end
    end
end

reg [DISTRICT_NUM-1:0] program_stack_flag2 ;
always @(posedge Power_on or posedge iWE) begin
    if ( Power_on ) begin
        program_stack_flag2 <= {DISTRICT_NUM{1'b0}} ;
    end
    else if ( {iCE,oRY_BY,iRE}===3'b011 ) begin
        if ( {iCLE,iALE}===2'b10 ) begin
            if ( ((iIO === CMD_AUTO_PROGRAM_TRUE) || (iIO === CMD_AUTO_PROGRAM_MULTI))
                 && (iWP === 1'b1) ) begin
                program_stack_flag2 <= program_stack_flag ;
            end
        end
    end
end

//------------------------------------------------------------------------------
// Flag indicating selected District(for Erase)
//------------------------------------------------------------------------------
// erase_stack_flag   : register of 4bits(bit0 to bit3)
//                      for Erase operation, same definition as program_stack_flag.
//
//------------------------------------------------------------------------------
reg [DISTRICT_NUM-1:0] erase_stack_flag ;
always @(posedge Power_on or posedge iWE) begin
    if ( Power_on ) begin
        erase_stack_flag <= {DISTRICT_NUM{1'b0}} ;
    end
    else if ( {iCE,oRY_BY,iRE}===3'b011 ) begin
        if ( {iCLE,iALE}===2'b10 ) begin
            if ( (iIO !== CMD_AUTO_BLOCK_ERASE_1 ) &&
                 (iIO !== CMD_STATUS_READ_1      ) &&
                 (iIO !== CMD_STATUS_READ_2      )    ) begin
                erase_stack_flag <= {DISTRICT_NUM{1'b0}} ;
            end
        end
        else if ( {iCLE,iALE,iRE}===3'b011 ) begin
            if ( MOD_AUTO_BLOCK_ERASE_1 ) begin
                if ( add_pos == 1 ) begin
                        erase_stack_flag[iIO[6:5]] <= 1'b1 ;
                end
            end
        end
    end
end

reg [DISTRICT_NUM-1:0] erase_stack_flag2 ;
always @(posedge Power_on or posedge iWE) begin
    if ( Power_on ) begin
        erase_stack_flag2 <= {DISTRICT_NUM{1'b0}} ;
    end
    else if ( {iCE,oRY_BY,iRE}===3'b011 ) begin
        if ( {iCLE,iALE}===2'b10 ) begin
            if ( (iIO === CMD_AUTO_BLOCK_ERASE_2) && (iWP === 1'b1) ) begin
                erase_stack_flag2 <= erase_stack_flag ;
            end
        end
    end
end


//------------------------------------------------------------------------------
// Input to Data Register Pointer DPNT and increment
//------------------------------------------------------------------------------
//
//    This is a pointer for addressing Data Registers.
//    Since Data Registers have 528 words, 10bit width is necessary for this register.
//    Lower 8bits are input value of IO by address input.
//    Upper 2bits depend on Area,
//          in case of Area-A, 00
//          in case of Area-B, 01
//          in case of Area-C, 10
//
//    Data Register Pointer is set by address input basically, and is incremented by
//    Data Input and Data Read operation.
//
//------------------------------------------------------------------------------
always @(posedge iWE or posedge iRE )
    if ( {iCE,oRY_BY}===2'b01 ) begin

        //
        // WE signal rising
        //
        if ( {bWE,iWE,iRE}===3'b011 ) begin
            if ( {iCLE,iALE}===2'b01 ) begin
                if ( MOD_SERIAL_DATA_INPUT || MOD_READ_MODE ) begin
                     if (add_pos == 0 ) DPNT <= {area_c,area_b,iIO & (MOD_READ_MODE_3? 8'h0f : 8'hff)} ;
                end
                else if ( MOD_AUTO_BLOCK_ERASE_1 ) begin
                    if (add_pos == 1 ) DPNT <= {COL_BIT{1'bx}} ;
                end
                else if ( MOD_ID_READ ) begin
                    if (add_pos == 0 ) DPNT <= iIO[ID_ADD_BIT-1:0] ;
                end
            end
            else if ( {iCLE,iALE}===2'b00 ) begin
                if (MOD_SERIAL_DATA_INPUT) begin
                    if ( DPNT < COL_IN_PAGE ) DPNT <= DPNT + 1 ;
                    if ( DPNT == COL_IN_PAGE-1 ) DIN_COMPLETE <= 1'b1 ;
                    if ( ^DPNT === 1'bx     ) DPNT <= {COL_BIT{1'bx}} ;
                end
            end
        end

        //
        // RE signal rising
        //
        if ( {bRE,iRE,iWE}===3'b011 ) begin
            if ( {iCLE,iALE}===2'b00 ) begin
                if (MOD_READ_MODE && BUSY_by_read_sched) begin
                    if ( DPNT < COL_IN_PAGE - 1 ) begin
                            DPNT <= DPNT + 1 ;
                    end
                    else if ( DPNT == COL_IN_PAGE - 1 ) begin
                        if ( (RADD>>ADD_COL) < {(BLK_BIT+PAG_BIT){1'b1}} ) begin
//                            DPNT <= (area_c) ? (AREA_SIZ_A + AREA_SIZ_B) : 0 ;
                        end
                    end
                    else if ( ^DPNT === 1'bx ) begin
                        DPNT <= {COL_BIT{1'bx}} ;
                    end
                end
            end
        end
    end


//------------------------------------------------------------------------------
// Input to Data Register
//------------------------------------------------------------------------------
//
//      This function describes that Data input to Data Register in Serial Data Input and
//      Data transfer from memory cell to Data Register.
//
//      At Data input, DATA0,DATA1,DATA2 and DATA3 are used and corresponding to each
//      District.
//
//------------------------------------------------------------------------------
always @(posedge iWE or BUSY_by_read ) begin

   //
   // WE signal rising
   //
   if ( {bWE,iWE,iRE}===3'b011 ) begin
        if ( {iCE,iCLE,iALE,oRY_BY}===4'b0101 ) begin
           if ( ( iIO == CMD_SERIAL_DATA_INPUT ) || ( iIO == CMD_RESET ) ) begin
                for ( column=0 ; column < COL_IN_PAGE ; column=column+1 )
                begin
                    if(~program_stack_flag[0]) DATA0[column]<={D_WIDTH{1'b1}} ;
                    if(~program_stack_flag[1]) DATA1[column]<={D_WIDTH{1'b1}} ;
                    if(~program_stack_flag[2]) DATA2[column]<={D_WIDTH{1'b1}} ;
                    if(~program_stack_flag[3]) DATA3[column]<={D_WIDTH{1'b1}} ;
                end
           end
        end
        if ( {iCE,iCLE,iALE,oRY_BY}===4'b0001 ) begin
            if (MOD_SERIAL_DATA_INPUT) begin
                if ( DPNT < COL_IN_PAGE ) begin
                    if (district==0) DATA0[DPNT] <= iIO ;
                    if (district==1) DATA1[DPNT] <= iIO ;
                    if (district==2) DATA2[DPNT] <= iIO ;
                    if (district==3) DATA3[DPNT] <= iIO ;
                end
                if ( ^DPNT === 1'bx ) begin
                    for ( column=0 ; column < COL_IN_PAGE ; column=column+1 )
                    begin
                        if (district==0) DATA0[column] <= {D_WIDTH{1'bx}} ;
                        if (district==1) DATA1[column] <= {D_WIDTH{1'bx}} ;
                        if (district==2) DATA2[column] <= {D_WIDTH{1'bx}} ;
                        if (district==3) DATA3[column] <= {D_WIDTH{1'bx}} ;
                    end
                end
            end
        end
   end

   //
   // BUSY_by_read signal falling
   //
   if ( {bBUSY_by_read,BUSY_by_read}===2'b10 ) begin
            for ( column = 0 ; column < COL_IN_PAGE ; column=column+1 )
                DATA0[column] <= {D_WIDTH{1'b1}} ;
   end

   //
   // BUSY_by_read signal rising
   //
   if ( {bBUSY_by_read,BUSY_by_read}===2'b01 ) begin
       if ( BUSY_by_ce ) begin
            for ( column = 0 ; column < COL_IN_PAGE ; column=column+1 )
                DATA0[column] <=
                    ( ^RADD === 1'bx )
                    ? {D_WIDTH{1'bx}}
                    : MEM[(RADD[(ADD_BIT-1):(ADD_COL)]<<COL_BIT)+column] ;
       end
   end
end

//------------------------------------------------------------------------------
// Input to Memory Cell
//------------------------------------------------------------------------------
//      Describe the function of Write(Program/Erase) to memory cell.
//      mem_write task is formed as following;
//      Form:   mem_write(mode,address)
//
//------------------------------------------------------------------------------
reg RSTAT_clear ;
always @(posedge Power_on or posedge iWE)
    if (Power_on) begin
        RSTAT[4:0] = {5'b00000} ;
        RSTAT_clear <= 1'b1 ;
        mem_init ;  // initializing memory
    end
    else if ( {iCE,iCLE,iRE}===3'b011 )
        if ( iIO === CMD_RESET  ) begin
            RSTAT[4:0] = {5'b00000} ;
            RSTAT_clear <= 1'b1 ;
            if ( ~BUSY_by_program ) begin
                if (program_stack_flag2[0]) mem_write(XPROGRAM,RADD0) ;
                if (program_stack_flag2[1]) mem_write(XPROGRAM,RADD1) ;
                if (program_stack_flag2[2]) mem_write(XPROGRAM,RADD2) ;
                if (program_stack_flag2[3]) mem_write(XPROGRAM,RADD3) ;
                program_stack_flag2 <= {DISTRICT_NUM{1'b0}} ;
            end
            if ( ~BUSY_by_erase ) begin
                if (erase_stack_flag2[0]) mem_write(XERASE,RADD0) ;
                if (erase_stack_flag2[1]) mem_write(XERASE,RADD1) ;
                if (erase_stack_flag2[2]) mem_write(XERASE,RADD2) ;
                if (erase_stack_flag2[3]) mem_write(XERASE,RADD3) ;
                erase_stack_flag2 <= {DISTRICT_NUM{1'b0}} ;
            end
        end
        else if ( MOD_SERIAL_DATA_INPUT && ( (iIO === CMD_AUTO_PROGRAM_TRUE ) ||
                                             (iIO === CMD_AUTO_PROGRAM_MULTI) ) )
        begin
            if (iWP) begin
                if (RSTAT_clear) RSTAT[4:0] = {5'b00000} ;
                if (program_stack_flag[0]) mem_write(PROGRAM,RADD0) ;
                if (program_stack_flag[1]) mem_write(PROGRAM,RADD1) ;
                if (program_stack_flag[2]) mem_write(PROGRAM,RADD2) ;
                if (program_stack_flag[3]) mem_write(PROGRAM,RADD3) ;
                if ( iIO === CMD_AUTO_PROGRAM_TRUE  ) RSTAT_clear <= 1'b1 ;
                if ( iIO === CMD_AUTO_PROGRAM_MULTI ) RSTAT_clear <= 1'b0 ;
            end
        end
        else if ( MOD_AUTO_BLOCK_ERASE_1 && (iIO===CMD_AUTO_BLOCK_ERASE_2) )
        begin
            if (iWP) begin
                RSTAT[4:0] = {5'b00000} ;
                if (erase_stack_flag[0]) mem_write(ERASE,RADD0) ;
                if (erase_stack_flag[1]) mem_write(ERASE,RADD1) ;
                if (erase_stack_flag[2]) mem_write(ERASE,RADD2) ;
                if (erase_stack_flag[3]) mem_write(ERASE,RADD3) ;
            end
        end

//------------------------------------------------------------------------------
// Generate Ready/Busy signal
//------------------------------------------------------------------------------
always @(posedge Power_on or posedge iWE or posedge iRE )
    if (Power_on)
    begin
        BUSY_by_reset      <= 1'b1 ;
        BUSY_by_read       <= 1'b1 ;
        BUSY_by_read_sched <= 1'b1 ;
        BUSY_by_program    <= 1'b1 ;
        BUSY_by_erase      <= 1'b1 ;
        BUSY_by_ce         <= 1'b1 ;
    end
    //
    //
    //
    else if ( {iCE,oRY_BY}==2'b00 ) begin
        if ( {bWE,iWE,iRE}==3'b011 ) begin
            if ( {iCLE,iALE}===2'b10 ) begin
                if ( (iIO == CMD_RESET) && (BUSY_by_reset===1'b1) ) begin
                    BUSY_by_reset <= 1'b0 ;
                    if ( MOD_AUTO_BLOCK_ERASE_2 ) begin
                        BUSY_by_reset       <= #(`tRST_erase)   1'b1 ;
                        BUSY_by_erase       <= #(`tRST_erase)   1'b1 ;
                    end
                    else if ( MOD_AUTO_PROGRAM ) begin
                        BUSY_by_reset       <= #(`tRST_program) 1'b1 ;
                        BUSY_by_program     <= #(`tRST_program) 1'b1 ;
                    end
                    else begin
                        BUSY_by_reset       <= #(`tRST_read)    1'b1 ;
                        BUSY_by_read        <= #(`tRST_read)    1'b1 ;
                   end
                end
            end
        end
    end
    else if ( {iCE,oRY_BY}==2'b01 ) begin
        if ( {bWE,iWE,iRE}==3'b011 ) begin
            if ( {iCLE,iALE}===2'b10 ) begin
                if ( iIO === CMD_RESET ) begin
                    BUSY_by_reset       <= #(`tWB)       1'b0 ;
                    BUSY_by_reset       <= #(`tRST_read) 1'b1 ;
                end
            end

            if ( MOD_READ_MODE && ({iCLE,iALE}===2'b01) ) begin
                if ( add_pos == 3 ) begin
                    BUSY_by_read        <= #(`tWB)       1'b0 ;
                    BUSY_by_read        <= #(`tR)        1'b1 ;
                end
            end

            if ( MOD_SERIAL_DATA_INPUT && ({iCLE,iALE}===2'b10) ) begin
                if ( (iIO === CMD_AUTO_PROGRAM_TRUE) && (iWP === 1'b1) ) begin
                    BUSY_by_program     <= #(`tWB)       1'b0 ;
                    BUSY_by_program     <= #(`tPROG)     1'b1 ;
                end
                if ( (iIO === CMD_AUTO_PROGRAM_DUMMY) && (iWP === 1'b1) ) begin
                    BUSY_by_program     <= #(`tWB)       1'b0 ;
                    BUSY_by_program     <= #(`tDBSY)     1'b1 ;
                end
                if ( (iIO === CMD_AUTO_PROGRAM_MULTI) && (iWP === 1'b1) ) begin
                    BUSY_by_program     <= #(`tWB)       1'b0 ;
                    BUSY_by_program     <= #(`tMBPBSY)   1'b1 ;
                end
            end

            if ( MOD_AUTO_BLOCK_ERASE_1 && ({iCLE,iALE}===2'b10) ) begin
                if ( (iIO === CMD_AUTO_BLOCK_ERASE_2) && (iWP === 1'b1) ) begin
                    BUSY_by_erase       <= #(`tWB)       1'b0 ;
                    BUSY_by_erase       <= #(`tBERASE)   1'b1 ;
                end
            end
        end
        if ( {bRE,iRE,iWE}===3'b011 ) begin
            if ( MOD_READ_MODE && ({iCLE,iALE}===2'b00) ) begin
                if ( (DPNT==COL_IN_PAGE-1) ) begin
                    if ( (RADD>>ADD_COL) < {(BLK_BIT+PAG_BIT){1'b1}} ) begin
                        BUSY_by_read_sched  <=              1'b0 ;
                    end
                end
            end
        end
    end


always @( negedge BUSY_by_read ) begin
        if ( BUSY_by_read_sched  === 1'b0 ) begin
            if ( (RADD>>ADD_COL) < {(BLK_BIT+PAG_BIT){1'b1}} ) begin
                DPNT <= (area_c) ? (AREA_SIZ_A + AREA_SIZ_B) : 0 ;
                RADD <= RADD + (1<<ADD_COL) ;
            end
        end
end

always @( negedge BUSY_by_read_sched ) begin
    #(`tCERY) begin
        if ( iCE === 1'b0 ) begin
             BUSY_by_read        <= #((`tRB)-(`tCERY)) 1'b0 ;
             BUSY_by_read        <= #((`tR )-(`tCERY)) 1'b1 ;
             BUSY_by_read_sched  <= #((`tR )-(`tCERY)) 1'b1 ;
        end
        else begin
             BUSY_by_read_sched  <= #((`tRB)-(`tCERY)) 1'b1 ;
        end
    end
end

always @( posedge iCE ) begin
    if ( (BUSY_by_read===1'b0) && (BUSY_by_read_sched===1'b0) ) begin
         BUSY_by_ce         <=            1'b0 ;
         BUSY_by_ce         <= #(`tCRY)   1'b1 ;
         BUSY_by_read       <= #(`tCRY-1) 1'b1 ;
         BUSY_by_read_sched <= #(`tCRY-1) 1'b1 ;
    end
    else  if ( (BUSY_by_read===1'b0) && (BUSY_by_read_sched===1'b1) ) begin
         BUSY_by_ce         <=            1'b0 ;
         BUSY_by_ce         <= #(`tCRY)   1'b1 ;
         BUSY_by_read       <= #(`tCRY-1) 1'b1 ;
    end
    else  if ( (BUSY_by_read===1'b1) && (BUSY_by_read_sched===1'b0) ) begin
         BUSY_by_read_sched <= #(`tCRY) 1'b1 ;
    end
end

always @(BUSY_by_reset)   bBUSY_by_reset   <= BUSY_by_reset ;
always @(BUSY_by_read)    bBUSY_by_read    <= BUSY_by_read ;
always @(BUSY_by_program) bBUSY_by_program <= BUSY_by_program ;
always @(BUSY_by_erase)   bBUSY_by_erase   <= BUSY_by_erase ;
always @(BUSY_by_erase)   bBUSY_by_ce      <= BUSY_by_ce ;

assign oRY_BY = BUSY_by_reset & BUSY_by_read & BUSY_by_program & BUSY_by_erase &
                BUSY_by_ce ;

always @( MOD_SERIAL_DATA_INPUT ) begin
    DIN_COMPLETE = 1'b0 ;
end

always @( BUSY_by_read ) begin
    if ( Reset_on) begin
    	if ( BUSY_by_read==1'b0 )
    	read_ok = 1'b0 ;
    	else
    	read_ok = 1'b1 ;
	end
end

//------------------------------------------------------------------------------
// Status Register (bit8,bit7,bit6)
//------------------------------------------------------------------------------
initial            RSTAT[5] <= 1'b0 ;   // IO6
always @( oRY_BY ) RSTAT[6] <= oRY_BY ; // IO7
always @( iWP    ) RSTAT[7] <= iWP ;    // IO8

//------------------------------------------------------------------------------
// Generate output value and output enable signal
//------------------------------------------------------------------------------

reg xRE ;
always @(posedge iRE) begin
    xRE <=               iRE  ;
    xRE <= #(`tRHZ-`tOH) 1'b0 ;
end

// output enable signal oIO
assign #(`tOH) oIO = ({iCE,iRE,xRE,iWE}===4'b0001) ? (MOD_STATUS_READ_1)? RSTAT&(8'hc1) :
                                           (MOD_STATUS_READ_2)? RSTAT&(8'hdf) :
                                           (~oRY_BY          )?{D_WIDTH{1'bx}}:
                                           (MOD_READ_MODE    )? DATA0[DPNT]   :
                                           (MOD_ID_READ_1    )? RID1[RADD]    :
                                           (MOD_ID_READ_2    )? RID2[RADD]    :
                                           {D_WIDTH{1'bx}}
                                         : {D_WIDTH{1'bx}}
                                         ;

// tREA == tREAID == tRSTO

wire iCE_d ;
wire iRE_d ;

localbuf #(`tOH,`tREA) localbuf_RE (iRE_d,iRE) ;
localbuf #(`tCHZ,`tCSTO) localbuf_CE (iCE_d,iCE) ;
assign eIO = ( (iCE_d  === 1'b0) &&
               (iCLE   === 1'b0) &&
               (iALE   === 1'b0) &&
               (iRE_d  === 1'b0)
             ) ? 1'b1 : 1'b0 ;

//------------------------------------------------------------------------------
// Function checking Commands
//------------------------------------------------------------------------------
//         cmd_check returns '1' in case of valid command,
//                           '0' in case of invalid command.
//
//------------------------------------------------------------------------------
function cmd_check ;

    input [D_WIDTH-1:0] now_val ;
    input [D_WIDTH-1:0] new_val ;

    begin
        case (new_val)
            CMD_SERIAL_DATA_INPUT  : cmd_check = ( oRY_BY && iWP ) ? 1'b1 : 1'b0 ;
            CMD_READ_MODE_1        : cmd_check = ( oRY_BY )        ? 1'b1 : 1'b0 ;
            CMD_READ_MODE_2        : cmd_check = ( oRY_BY )        ? 1'b1 : 1'b0 ;
            CMD_READ_MODE_3        : cmd_check = ( oRY_BY )        ? 1'b1 : 1'b0 ;
            CMD_RESET              : cmd_check =                     1'b1        ;
            CMD_AUTO_PROGRAM_TRUE  : cmd_check = ( oRY_BY && iWP ) ? 1'b1 : 1'b0 ;
            CMD_AUTO_PROGRAM_DUMMY : cmd_check = ( oRY_BY && iWP ) ? 1'b1 : 1'b0 ;
            CMD_AUTO_PROGRAM_MULTI : cmd_check = ( oRY_BY && iWP ) ? 1'b1 : 1'b0 ;
            CMD_AUTO_BLOCK_ERASE_1 : cmd_check = ( oRY_BY && iWP ) ? 1'b1 : 1'b0 ;
            CMD_AUTO_BLOCK_ERASE_2 : cmd_check = ( oRY_BY && iWP ) ? 1'b1 : 1'b0 ;
            CMD_STATUS_READ_1      : cmd_check =                     1'b1        ;
            CMD_STATUS_READ_2      : cmd_check =                     1'b1        ;
            CMD_ID_READ_1          : cmd_check = ( oRY_BY )        ? 1'b1 : 1'b0 ;
            CMD_ID_READ_2          : cmd_check = ( oRY_BY )        ? 1'b1 : 1'b0 ;
            default                : begin cmd_check = 1'b0 ;
                                     if (!($test$plusargs("error_disable_00")||
                                           $test$plusargs("error_disable_all")) )
                                     begin
                                         $write("Error: [E-00] ") ;
                                         $write("Unkown Command ") ;
                                         $write("(%h)h ",new_val);
                                         $write("Input Ignore at %0t \n",
                                                 $time ) ;
                                     end
                                     end
        endcase
    end

endfunction

//------------------------------------------------------------------------------
// Task writing memory cells
//------------------------------------------------------------------------------
//
//  Form : mem_write(mode,address,purge)
//  Write to memory;
//         in case mode is PROGRAM, contens of selected Data Register of district are
//                                  transferred to the selected page.
//         in case of mode is ERASE, the selected block is erased.
//         in case of mode XPROGRAM, the selected page gets unknown value.
//         in case of mode XERASE, the selected block gets unknown value.
//
//------------------------------------------------------------------------------
task mem_write ;

    input [2:0]         mode ;
    input [ADD_BIT-1:0] add ;

    integer bit ;
    integer column ;
    integer page ;
    integer block ;
    integer tmp_add ;
    integer failbit ;
    integer val ;

    reg [1:0]         district ;

    begin

        district = add[15:14] ;
        block = add[(ADD_BIT-1):(PAG_BIT+ADD_COL)] ;
        scan_bad(block,val) ;

        if ( mode == XPROGRAM ) begin
            for ( column = 0 ; column < COL_IN_PAGE ; column=column+1 ) begin
                tmp_add = (add[(ADD_BIT-1):(ADD_COL)]<<COL_BIT)+column ;
                MEM[tmp_add] <= {D_WIDTH{1'bx}} ;
            end
        end

        if ( mode == XERASE   ) begin
            block_set(block,1'bx) ;
        end

        if ( (mode == PROGRAM) && (val !== 1) ) begin
            for ( column = 0 ; column < COL_IN_PAGE ; column=column+1 ) begin
                tmp_add = (add[(ADD_BIT-1):(ADD_COL)]<<COL_BIT)+column ;

                     scan_fail(tmp_add,failbit) ;
           
                if ( 8'h00 != failbit) begin 
                    RSTAT[0]          = 1'b1 ;
                    RSTAT[district+1] = 1'b1 ;
                    $display("MSG: address:%x bit:%0b is erase fail ... at %0tns",tmp_add,failbit,$time) ;
                end
                else begin
                    failbit = 8'b00000000 ;
                end

                MEM[tmp_add] <=
                    (district==0) ? (DATA0[column] & MEM[tmp_add]) ^ failbit :
                    (district==1) ? (DATA1[column] & MEM[tmp_add]) ^ failbit :
                    (district==2) ? (DATA2[column] & MEM[tmp_add]) ^ failbit :
                    (district==3) ? (DATA3[column] & MEM[tmp_add]) ^ failbit :
                    {D_WIDTH{1'bx}} ;
            end
        end

        if ( (mode == ERASE) && (val !== 1) ) begin

            $display("MSG: Block %0d Erase ...",block) ;

            for ( page=0 ; page < PAGE_IN_BLOCK ; page = page + 1 ) begin
                for ( column=0 ; column < COL_IN_PAGE ; column = column + 1 ) begin
                   tmp_add = (block<<(PAG_BIT+COL_BIT)) + (page<<(COL_BIT)) + (column) ;

                    MEM[tmp_add] <= {D_WIDTH{1'b1}} ;

                    scan_fail(tmp_add,failbit) ;
                    
                    if ( 8'h00 != failbit) begin 

                        RSTAT[0]          =  1'b1 ;
                        RSTAT[district+1] =  1'b1 ;
                        $display("MSG: address:%x bit:%0b is erase fail ... at %0tns",tmp_add,failbit,$time) ;
                        MEM[tmp_add] <= 8'hFF ^ failbit ;

                    end
                end
            end
        end
    end
endtask

//------------------------------------------------------------------------------
// Task Memory Initialize
//------------------------------------------------------------------------------
// If "MemoryInitEnable" defined  "1", whole CHIP data "1" except for Bad Block.
//------------------------------------------------------------------------------
task mem_init ;

    integer block ;
    integer val ;
    integer i ;

    if ( `MemoryInitEnable ) begin

        for ( block = 0  ; block < (1<<BLK_BIT) ; block = block + 1 ) begin
              scan_bad(block,val) ;
            if (val == 1) begin
            	block_set(block,1'b0) ;
                $display("MSG: Block %0d is Bad Block ...",block) ;
            end
            else
            	block_set(block,1'b1) ;
        end
    end
endtask

//------------------------------------------------------------------------------
// Task making whole 1 Block set
//------------------------------------------------------------------------------
task block_set ;
    input [(1<<BLK_BIT)-1:0] block ;
    input value ;

    integer column ;
    integer page ;
    integer tmp_add ;

    begin

            for ( page=0 ; page < PAGE_IN_BLOCK ; page = page + 1 ) begin
                for ( column=0 ; column < COL_IN_PAGE ; column = column + 1 ) begin
                   tmp_add = (block<<(PAG_BIT+COL_BIT)) + (page<<(COL_BIT)) + (column) ;

                MEM[tmp_add] <= {D_WIDTH{value}} ;

                end
            end
    end
endtask

//------------------------------------------------------------------------------
// Task scan fail
//------------------------------------------------------------------------------
task scan_fail ;
    input  [ADD_BIT-1:0] inadd ;
    output [7:0] fail_bit ;

    integer i ;

    begin
            fail_bit = 8'h00 ;
			// XXXXXXXX
//            for ( i=0 ; i < FAIL_NUM ; i = i + 1 ) begin
//                if( inadd == FAIL_ADD[i] )
//                     fail_bit = FAIL_BIT[i] ;
//            end
    end
endtask

//------------------------------------------------------------------------------
// Task scan block
//------------------------------------------------------------------------------
task scan_bad ;
    input  [BLK_BIT-1:0] inadd ;
    output val ;
    begin
            val = 0 ;
    end
endtask

//------------------------------------------------------------------------------
// Signal Operation time
//------------------------------------------------------------------------------
always @( WE ) begin
  if ( WE==1'b1) begin
      rWE = $time ;
      fWE2 = fWE ;
  end
  else begin
      fWE = $time ;
  end
end

always @( CE ) begin
  if ( CE==1'b1 ) begin
      rCE = $time ;
  end
  else begin
      fCE = $time ;
  end
end

always @( ALE ) begin
  if( ALE==1'b1 ) begin
      rALE = $time ;
  end
  else begin
      fALE = $time ;
  end
end

always @( CLE ) begin
  if( CLE==1'b1 ) begin
      rCLE = $time ;
  end
  else begin
      fCLE = $time ;
  end
end

always @( RE ) begin
  if ( RE==1'b1) begin
      rRE = $time ;
      fRE2 = fRE ;
  end
  else begin
      fRE = $time ;
  end
end

always @( RY_BY ) begin
  if( RY_BY==1'b1 ) begin
      rRY_BY = $time ;
  end
  else begin
      fRY_BY = $time ;
  end
end

always @( IO ) begin
      rfIO = $time ;
end

always @( WP ) begin
  if ( WP==1'b1 ) begin
      rWP = $time ;
  end
  else begin
      fWP = $time ;
  end
end


// tCH Check
always @( rCE or fCE ) begin
  if( $time > 0 ) begin
    if ( CE==1'b1 ) begin
        if( $time-rWE < `tCH ) begin
          $write("Error: %0tns : CE Hold Time (tCH) was not proper.\n",$time) ;
        end
    end
    else if($time-rWE < `tWHC && MOD_STATUS_READ ) begin
          $write("Error: %0tns : WE High to CE Low (tWHC) was not proper.\n",$time) ;
    end
  end
end

// tCLH Check
always @( rCLE or fCLE ) begin
  if( $time > 0 ) begin
      if( $time-rWE < `tCLH) begin
        $write ("Error: %0tns : CLE Hold Time (tCLH/at command) was not proper.\n",$time) ;
      end
  end
end

// tALH Check
always @( rALE or fALE ) begin
  if( $time > 0 ) begin
      if( $time-rWE < `tALH) begin
        $write ("Error: %0tns : ALE Hold Time (tALH) was not proper.\n",$time) ;
      end
  end
end

// tDS, tWP, tWH, tWC Check
always @( WE ) begin      
  if( $time > 0 ) begin
    if( WE==1'b1 ) begin
        if( $time-rfIO < `tDS) begin 
          # 1;
          if (CE === 0)
              $write ("Error: %0tns : Data Setup Time (tDS) was not proper.\n",$time) ;
        end
        if( $time-fWE < `tWP) begin  
          # 1;
          if (CE === 0)
              $write ("Error: %0tns : Write Pulse width (tWP) was not proper.\n",$time) ;
        end
    end
    else if( WE==1'b0 ) begin
        if( $time-rWE < `tWH) begin  
          $write ("Error: %0tns : WE High Hold Time (tWH) was not proper.\n",$time) ;
        end
        if( $time-fWE2 < `tWC) begin 
          $write ("Error: %0tns : Write Cycle Time (tWC) was not proper.\n",$time) ;
        end
    end
  end
end

// tWW Check
always @( fWE ) begin 
  if( $time > 0 ) begin
        if( $time-rWP < `tWW) begin        // tWW(High)
          $write ("Error: %0tns : WP High to WE Low (tWW) was not proper.\n",$time) ;
        end
        else if( $time-fWP < `tWW) begin     // tWW(Low)
          $write ("Error: %0tns : WP Low to WE Low (tWW) was not proper.\n",$time) ;
        end
  end
end

// tRP, tREH, tRC Check
always @( RE ) begin
  if( $time > 0 ) begin
    if( RE==1'b1 ) begin
        if($time-fRE < `tRP) begin
		  # 1;
		  if (CE === 0)
              $write("Error: %0tns : Read Pulse width (tRP) was not proper.\n",$time) ;
        end
    end
    else if( RE==1'b0 ) begin
        if($time-rRE < `tREH) begin
          $write("Error: %0tns : Read High Hold Time (tREH) was not proper.\n",$time) ;
        end
        if($time-fRE2 < `tRC) begin
          $write("Error: %0tns : Read Cycle time (tRC) was not proper.\n",$time) ;
        end
    end
  end
end

// tRR, tWHR, tAR1, tAR2 Check
always @( fRE ) begin 
  if( $time > 0 ) begin
    if($time-rRY_BY < `tRR) begin
      $write("Error: %0tns : Ready to RE Falling edge (tRR) was not proper.\n",$time) ;
    end
    if($time-rWE < `tWHR && MOD_STATUS_READ ) begin
      $write("Error: %0tns : WE High to RE Low (tWHR) was not proper.\n",$time) ;
    end

    if( MOD_ID_READ ) begin
        if($time-fALE < `tAR1) begin
			if (CE === 0)
	            $write("Error: %0tns : ALE Low to RE Low (tAR1) was not proper.\n",$time) ;
        end
        if($time-fCE < `tCR && (MOD_STATUS_READ==1'b0) ) begin
            $write("Error: %0tns : CE Low to RE Low (tCR) was not proper.\n",$time) ;
        end
    end
    else if( MOD_READ_MODE ) begin
        if($time-fALE < `tAR2) begin
            $write("Error: %0tns : ALE Low to RE Low (tAR2) was not proper.\n",$time) ;
        end
    end
  end
end

// tDH Check
always @( IO ) begin  
  if( $time > 0 ) begin
    if( $time-rWE < `tDH ) begin
        # 1;
        if (CE === 0)
           $write("Error: %0tns : Data Hold time (tDH) was not proper.\n",$time) ;
    end
  end
end

// Setup/Hold timing 
// tCLS Check 
always @( rCLE or fCLE) begin 
  if( $time > 0  && WE==1'b0 && $time!=fWE ) begin
    if( ALE==1'b1 || (MOD_SERIAL_DATA_INPUT && add_pos > 0) ) begin
      if( CLE==1'b0 )
        $write("Error: %0tns : CLE Setup Time (tCLS/at address or data in) was not proper.\n",$time) ; // ADD
    end
    else begin
      if( CLE==1'b1 )
        $write("Error: %0tns : CLE Setup Time (tCLS/at command) was not proper.\n",$time) ; // COM
    end
  end
end

// tCLH Check 
always @( rCLE or fCLE) begin 
  if( $time > 0  && WE==1'b0 && $time!=fWE ) begin
    if( ALE==1'b1 || (MOD_SERIAL_DATA_INPUT && add_pos > 0) ) begin
      if( $time-rWE < `tCLH )
        $write("Error: %0tns : CLE Hold Time (tCLH/at address or data in) was not proper.\n",$time) ;
    end
    else begin
      if( CLE==1'b0 )
        $write("Error: %0tns : CLE Hold Time (tCLH/at command) was not proper.\n",$time) ;
    end
  end
end

// tALS Check 
always @( rALE or fALE) begin 
  if( $time > 0  && WE==1'b0 && $time!=fWE ) begin
    if( CLE==1'b1 || (MOD_SERIAL_DATA_INPUT && add_pos > 0) ) begin
      if( ALE==1'b0 )
        $write("Error: %0tns : ALE Setup Time (tALS/at command or data in) was not proper.\n",$time) ;
    end
    else begin
      if( ALE==1'b1 )
        $write("Error: %0tns : ALE Setup Time (tALS/at address) was not proper.\n",$time) ;
    end
  end
end

// tALH Check 
always @( rALE or fALE) begin 
  if( $time > 0  && WE==1'b0 && $time!=fWE ) begin
    if( CLE==1'b1 || (MOD_SERIAL_DATA_INPUT && add_pos > 0) ) begin
      if( ALE==1'b1 )
        $write("Error: %0tns : ALE Hold Time (tALH/at command or data in) was not proper.\n",$time) ;
    end
    else begin
      if( ALE==1'b0 )
        $write("Error: %0tns : ALE Hold Time (tALH/at address) was not proper.\n",$time) ;
    end
  end
end

// tCS Check 
always @( fCE) begin
  if( $time > 0  && WE==1'b0 && $time!=fWE ) begin
          $write("Error: %0tns : CE Setup Time (tCS) was not proper.\n",$time) ;
  end
end

// tCH Check 
always @( posedge CE) begin
  if( $time > 0  && WE==1'b0 ) begin
          $write("Error: %0tns : CE Hold Time (tCH) was not proper.\n",$time) ;
  end
end

// tAR1, tAR2 Check 
always @( fALE ) begin
  if( $time > 0 && RE==1'b0 && $time!=fRE )begin
      if( MOD_ID_READ ) begin
          $write("Error: %0tns : ALE Low to RE Low (tAR1/at ID Read) was not proper.\n",$time) ;
      end
      else if( MOD_READ_MODE ) begin
          $write("Error: %0tns : ALE Low to RE Low (tAR2/at Read Mode) was not proper.\n",$time) ;
      end
  end
end

// tCR Check 
always @( fCE ) begin
  if( $time > 0 && RE==1'b0 && $time!=fRE )begin
      if( MOD_ID_READ ) begin
          $write("Error: %0tns : CE Low to RE Low (tCR/at ID Read) was not proper.\n",$time) ;
      end
  end
end

// tCLS Check 
always @( fCLE ) begin
  if( $time > 0 && RE==1'b0 && $time!=fRE )begin
      if( MOD_STATUS_READ ) begin
          $write("Error: %0tns : CLE Setup Time (tCLS/at Status Read) was not proper.\n",$time); // ST READ
      end
  end
end

//Warning Message
always @( negedge RE ) begin
  if( MOD_READ_MODE ) begin
    if( MOD_STATUS_READ==1'b0 ) begin
        if( !read_ok ) begin
          $write("Error: %0tns : RE should be input after address input.\n",$time) ;
        end
        if( RY_BY==1'b0 ) begin
          $write("Error: %0tns : RE should be fix to 'H' while the device is in busy state.\n",$time) ;
        end
    end
  end
end

// tCLS Check 
always @( posedge WE ) begin
  if( CE==1'b0 && RE==1'b1 && CLE==1'b0 && ALE==1'b0 && DIN_COMPLETE==1'b1 ) begin
    $write("Error: %0tns : When reached last column address, /WE should not be toggle.\n",$time) ;
  end
end

// tCLS Check 
always @( posedge CE ) begin
  if( MOD_READ_MODE ) begin
// frank;
// this is bogus, it does not handle terminations;
    // XXX $write("Error: %0tns : /CE was set to 'H'  while the device was in read operation.\n",$time) ;
    $write("Warning: %0tns : cmd terminated\n", $time);
  end
end

// tCLS Check 
always @( negedge RE or posedge CLE or posedge ALE ) begin
  if( CE==1'b0 && RE==1'b0 && (MOD_STATUS_READ==1'b0) ) begin
    if( CLE!=1'b0 || ALE!=1'b0 ) begin
      $write("Error: %0tns : Illegal operation. CLE=0 and ALE=0 was not selected in read mode.\n",$time) ;
      read_flg = 1'b1 ;
    end
  end
end

always @(IO) begin
    if ( {IO} === {D_WIDTH{1'bz}})
    IO_hiz = $time ;
end

`ifdef TOSHIBA_ORIGINAL
always @( fRE ) begin
  if( ($time > 0 && {IO}!=={D_WIDTH{1'bz}}) ) begin
        $write ("Error: %0tns: Timing violation tIR\n",$time) ;
    end
end
`endif

endmodule

module localbuf (z,a) ;
parameter rt = 0 ;
parameter ft = 0 ;
output z ;
input  a ;
reg    z ;
always @ (posedge a) z <= #(rt) a ;
always @ (negedge a) z <= #(ft) a ;
endmodule