sudp_mode.v
3.12 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/*
*************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************
*/
/*
*************************************************************************
* *
* Project Reality *
* *
* module: sudp_mode.v *
* description: 32 bit 3 input or, one common input. *
* *
* designer: Phil Gossett *
* date: 4/7/95 *
* *
*************************************************************************
*/
// $Id: sudp_mode.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
module sudp_mode (s, a, b, z) ;
input s;
input [31:0] a;
input [31:0] b;
output [31:0] z;
wire sa;
wire sb;
wire sc;
wire sd;
ni01d5 nisa (.i(s), .z(sa));
ni01d5 nisb (.i(s), .z(sb));
ni01d5 nisc (.i(s), .z(sc));
ni01d5 nisd (.i(s), .z(sd));
or03d1 or0 (.z(z[0]), .a1(a[0]), .a2(b[0]), .a3(sa));
or03d1 or1 (.z(z[1]), .a1(a[1]), .a2(b[1]), .a3(sa));
or03d1 or2 (.z(z[2]), .a1(a[2]), .a2(b[2]), .a3(sa));
or03d1 or3 (.z(z[3]), .a1(a[3]), .a2(b[3]), .a3(sa));
or03d1 or4 (.z(z[4]), .a1(a[4]), .a2(b[4]), .a3(sa));
or03d1 or5 (.z(z[5]), .a1(a[5]), .a2(b[5]), .a3(sa));
or03d1 or6 (.z(z[6]), .a1(a[6]), .a2(b[6]), .a3(sa));
or03d1 or7 (.z(z[7]), .a1(a[7]), .a2(b[7]), .a3(sa));
or03d1 or8 (.z(z[8]), .a1(a[8]), .a2(b[8]), .a3(sb));
or03d1 or9 (.z(z[9]), .a1(a[9]), .a2(b[9]), .a3(sb));
or03d1 or10 (.z(z[10]), .a1(a[10]), .a2(b[10]), .a3(sb));
or03d1 or11 (.z(z[11]), .a1(a[11]), .a2(b[11]), .a3(sb));
or03d1 or12 (.z(z[12]), .a1(a[12]), .a2(b[12]), .a3(sb));
or03d1 or13 (.z(z[13]), .a1(a[13]), .a2(b[13]), .a3(sb));
or03d1 or14 (.z(z[14]), .a1(a[14]), .a2(b[14]), .a3(sb));
or03d1 or15 (.z(z[15]), .a1(a[15]), .a2(b[15]), .a3(sb));
or03d1 or16 (.z(z[16]), .a1(a[16]), .a2(b[16]), .a3(sc));
or03d1 or17 (.z(z[17]), .a1(a[17]), .a2(b[17]), .a3(sc));
or03d1 or18 (.z(z[18]), .a1(a[18]), .a2(b[18]), .a3(sc));
or03d1 or19 (.z(z[19]), .a1(a[19]), .a2(b[19]), .a3(sc));
or03d1 or20 (.z(z[20]), .a1(a[20]), .a2(b[20]), .a3(sc));
or03d1 or21 (.z(z[21]), .a1(a[21]), .a2(b[21]), .a3(sc));
or03d1 or22 (.z(z[22]), .a1(a[22]), .a2(b[22]), .a3(sc));
or03d1 or23 (.z(z[23]), .a1(a[23]), .a2(b[23]), .a3(sc));
or03d1 or24 (.z(z[24]), .a1(a[24]), .a2(b[24]), .a3(sd));
or03d1 or25 (.z(z[25]), .a1(a[25]), .a2(b[25]), .a3(sd));
or03d1 or26 (.z(z[26]), .a1(a[26]), .a2(b[26]), .a3(sd));
or03d1 or27 (.z(z[27]), .a1(a[27]), .a2(b[27]), .a3(sd));
or03d1 or28 (.z(z[28]), .a1(a[28]), .a2(b[28]), .a3(sd));
or03d1 or29 (.z(z[29]), .a1(a[29]), .a2(b[29]), .a3(sd));
or03d1 or30 (.z(z[30]), .a1(a[30]), .a2(b[30]), .a3(sd));
or03d1 or31 (.z(z[31]), .a1(a[31]), .a2(b[31]), .a3(sd));
endmodule // sudp_mode