/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vmult.v,v 1.1 2002/03/28 00:26:14 berndt Exp $

module vmult(
	      vum_mplcnd_mu,
	      vum_mplr_mu,
	      vum_sgnmplcnd_mu,
	      vum_sgnmplr_mu,
	      vum_shiftleft1_mu,
	      vum_carryupper_mu,
	      vum_carrylower_mu,
	      vum_sumupper_mu,
	      vum_sumlower_mu,
	      vum_coh_cla_acc,
	      vum_col_cla_acc,
	      clk
	     );

input [15:0]  vum_mplcnd_mu;    	// multiplicand
input [15:0]  vum_mplr_mu;		// multiplier
input	      vum_sgnmplcnd_mu;  	// multiplicand is signed
input	      vum_sgnmplr_mu;           // multiplier is signed
input	      vum_shiftleft1_mu;	// left shift by 1 of carry and sum
input 	      clk;			// clk

output [15:0] vum_carryupper_mu;	// carry upper
output [15:0] vum_carrylower_mu;	// carry lower
output [15:0] vum_sumupper_mu;		// sum upper
output [15:0] vum_sumlower_mu;		// sum lower
output 	      vum_coh_cla_acc;		// Carry LookAhead off bit 31
output 	      vum_col_cla_acc;		// Carry LookAhead off bit 15

wire [5:0] mp;

// a[15:0] multiplicand
// b[15:0] multiplier
// as : a is signed
// bs : b is signed

wire [15:0] a = vum_mplcnd_mu;
wire [15:0] b = vum_mplr_mu;
wire as = vum_sgnmplcnd_mu;
wire bs = vum_sgnmplr_mu;
wire shiftl1 = vum_shiftleft1_mu;


wire sea = as & a[15]; //SignExtend A 
wire tc = bs & b[15]; 

//wire seap,sea;
//wire tcp,tc;
//an02d2  useap(.z(seap),.a1(as), .a2(a[15]));
//in01d5  usea(.zn(sea),.i(seap));
//an02d2  utcp(.z(tcp),.a1(bs), .a2(b[15]));
//in01d5  utc(.zn(tc),.i(tcp));

wire [16:0] p0  = {sea,a} & {17{b[0] }}; 
wire [16:0] p1  = {sea,a} & {17{b[1] }}; 
wire [16:0] p2  = {sea,a} & {17{b[2] }}; 
wire [16:0] p3  = {sea,a} & {17{b[3] }}; 
wire [16:0] p4  = {sea,a} & {17{b[4] }}; 
wire [16:0] p5  = {sea,a} & {17{b[5] }}; 
wire [16:0] p6  = {sea,a} & {17{b[6] }}; 
wire [16:0] p7  = {sea,a} & {17{b[7] }}; 
wire [16:0] p8  = {sea,a} & {17{b[8] }}; 
wire [16:0] p9  = {sea,a} & {17{b[9] }}; 
wire [16:0] p10 = {sea,a} & {17{b[10]}}; 
wire [16:0] p11 = {sea,a} & {17{b[11]}}; 
wire [16:0] p12 = {sea,a} & {17{b[12]}}; 
wire [16:0] p13 = {sea,a} & {17{b[13]}}; 
wire [16:0] p14 = {sea,a} & {17{b[14]}}; 
wire [16:0] p15 = {sea,a} & {17{b[15]}}; 
wire [16:0] tc15 = p15 ^ {17{tc}};
/**************************************************/
wire [17:0] sb, cb;
wire [17:0] sa, ca;

assign mp[0] = p0[0];
assign mp[1] = sa[0];

vmult_csa18  csa_a(
	           .co(ca[17:0]),
	           .s (sa[17:0]),
	           //
	           .ci({p0[16],p0[16],p0[16:1]}),
	           .b ({p1[16],p1[16:0]}),
	           .a ({p2[16:0],1'b0})
	          );
vmult_csa18  csa_b(
	           .co(cb[17:0]),
	           .s (sb[17:0]),
	           //
	           .ci({sa[17],sa[17:1]}),
	           .b (ca[17:0]),
	           .a ({p3[16:0],1'b0})
	          );

/**************************************************/
wire [18:0] sc;
wire [17:0] cc;
wire [19:0] sd;
wire [17:0] cd;

assign sc[0] = p4[0];
assign sd[0] = sc[0];
assign sd[1] = sc[1];

vmult_csa18  csa_c(
	           .co(cc[17:0]),
	           .s (sc[18:1]),
	           //
	           .a ({p4[16],p4[16],p4[16:1]}),
	           .b ({p5[16],p5[16:0]}),
	           .ci({p6[16:0],1'b0})
	          );
vmult_csa18  csa_d(
	           .co(cd[17:0]),
	           .s (sd[19:2]),
	           //
	           .ci({sc[18],sc[18:2]}),
	           .b (cc[17:0]),
	           .a ({p7[16:0],1'b0})
	          );

/**************************************************/
wire [18:0] se;
wire [17:0] ce;
wire [19:0] sf;
wire [17:0] cf;

assign se[0] = p8[0];
assign sf[0] = se[0];
assign sf[1] = se[1];

vmult_csa18  csa_e(
	           .co(ce[17:0]),
	           .s (se[18:1]),
	           //
	           .ci({p8[16],p8[16],p8[16:1]}),
	           .b ({p9[16],p9[16:0]}),
	           .a ({p10[16:0],1'b0})
	          );
vmult_csa18  csa_f(
	           .co(cf[17:0]),
	           .s (sf[19:2]),
	           //
	           .ci({se[18],se[18:2]}),
	           .b (ce[17:0]),
	           .a ({p11[16:0],1'b0})
	          );

/**************************************************/
wire [18:0] sg;
wire [17:0] cg;
wire [19:0] sh;
wire [18:0] ch; //ch[18] falls off the edge


assign sg[0] = p12[0];
assign sh[0] = sg[0];

vmult_csa18  csa_g(
	           .co(cg[17:0]),
	           .s (sg[18:1]),
	           //
	           .ci({p12[16],p12[16],p12[16:1]}),
	           .b ({p13[16],p13[16:0]}),
	           .a ({p14[16:0],tc})
	          );
vmult_csa19  csa_h(
	           .co(ch[18:0]),
	           .s (sh[19:1]),
	           //
	           .ci({sg[18],sg[18:1]}),
	           .b ({cg[17:0],1'b0}),
	           .a ({tc15[16:0],tc,tc})
	          );
/**************************************************/
/**************************************************/
wire [21:0] si;
wire [21:0] ci;
wire [21:0] sj;
wire [21:0] cj;

assign mp[2] = sb[0];
assign mp[3] = si[0];

vmult_ha	ha_i3(.co(ci[3]),.s(si[3]),.a(sb[4]),.b(cb[3]));
vmult_ha	ha_i2(.co(ci[2]),.s(si[2]),.a(sb[3]),.b(cb[2]));
vmult_ha	ha_i1(.co(ci[1]),.s(si[1]),.a(sb[2]),.b(cb[1]));
vmult_ha	ha_i0(.co(ci[0]),.s(si[0]),.a(sb[1]),.b(cb[0]));

vmult_csa18  csa_i(
	           .co(ci[21:4]),
	           .s (si[21:4]),
	           //
	           .a ({{5{sb[17]}},sb[17:5]}),
	           .b ({{4{cb[17]}},cb[17:4]}),
	           .ci(cd[17:0])
	          );
vmult_csa22  csa_j(
	           .co(cj[21:0]),
	           .s (sj[21:0]),
	           //
	           .ci({si[21],si[21:1]}),
	           .b (ci[21:0]),
	           .a ({sd[19],sd[19],sd[19:0]})
	          );

/**************************************************/
wire [23:0] sk;
wire [20:0] ck; //ck[20] falls off the edge
wire [23:0] sl;
wire [19:0] cl; //cl[19] falls off the edge

assign sk[2:0] = sf[2:0]; 
assign sl[3:0] = sk[3:0]; 

vmult_ha	ha_k2(.co(ck[2]),.s(sk[5]),.a(sf[5]),.b(cf[2]));
vmult_ha	ha_k1(.co(ck[1]),.s(sk[4]),.a(sf[4]),.b(cf[1]));
vmult_ha	ha_k0(.co(ck[0]),.s(sk[3]),.a(sf[3]),.b(cf[0]));

vmult_csa18  csa_k(
	           .co(ck[20:3]),
	           .s (sk[23:6]),
	           //
	           .ci({{4{sf[19]}},sf[19:6]}),
	           .b ({{3{cf[17]}},cf[17:3]}),
	           .a (ch[17:0])
	          );
vmult_csa20  csa_l(
	           .co(cl[19:0]),
	           .s (sl[23:4]),
	           //
	           .ci(sk[23:4]),
	           .b (ck[19:0]),
	           .a (sh[19:0])
	          );

/**************************************************/
wire [26:0] sm;
wire [26:0] cm; //cm[26] falls off the edge
wire [25:0] sn;
wire [25:0] cn; //cn[25] falls off the edge

assign mp[4] = sj[0];
assign mp[5] = sm[0];

vmult_ha	ha_m7(.co(cm[7]),.s(sm[7]),.a(sj[8]),.b(cj[7]));
vmult_ha	ha_m6(.co(cm[6]),.s(sm[6]),.a(sj[7]),.b(cj[6]));
vmult_ha	ha_m5(.co(cm[5]),.s(sm[5]),.a(sj[6]),.b(cj[5]));
vmult_ha	ha_m4(.co(cm[4]),.s(sm[4]),.a(sj[5]),.b(cj[4]));
vmult_ha	ha_m3(.co(cm[3]),.s(sm[3]),.a(sj[4]),.b(cj[3]));
vmult_ha	ha_m2(.co(cm[2]),.s(sm[2]),.a(sj[3]),.b(cj[2]));
vmult_ha	ha_m1(.co(cm[1]),.s(sm[1]),.a(sj[2]),.b(cj[1]));
vmult_ha	ha_m0(.co(cm[0]),.s(sm[0]),.a(sj[1]),.b(cj[0]));

vmult_csa19  csa_m(
	           .co(cm[26:8]),
	           .s (sm[26:8]),
	           //
	           .ci({{6{sj[21]}},sj[21:9]}),
	           .b ({{5{cj[21]}},cj[21:8]}),
	           .a (cl[18:0])
	          );

vmult_ha	ha_n1(.co(cn[1]),.s(sn[1]),.a(sm[2]),.b(cm[1]));
vmult_ha	ha_n0(.co(cn[0]),.s(sn[0]),.a(sm[1]),.b(cm[0]));

vmult_csa24  csa_n(
	           .co(cn[25:2]),
	           .s (sn[25:2]),
	           //
	           .ci(sm[26:3]),
	           .b (cm[25:2]),
	           .a (sl[23:0])
	          );

/*****************************************/
// Final output stage

wire [31:0] sum   = (shiftl1) ? {sn[24:0],mp[5:0],1'b0} : {sn[25:0],mp[5:0]};
wire [31:0] carry = (shiftl1) ? {cn[23:0],7'h0,1'b0}    : {cn[24:0],7'h0};

vmult_cla cla(.a(sum[31:7]), .b(carry[31:7]), .clk(clk), 
	      .coh(vum_coh_cla_acc), .col(vum_col_cla_acc));

assign vum_carryupper_mu = carry[31:16];
assign vum_carrylower_mu = carry[15:0];

assign vum_sumupper_mu = sum[31:16];
assign vum_sumlower_mu = sum[15:0];

endmodule

/*********************************************************
 * vmult_csa and vmult_ha module definitions
 ********************************************************/
module vmult_csa18 (co, s, a, b, ci);
parameter width = 18;
input  [width-1:0] a, b, ci;
output [width-1:0] co, s;

//assign s = a^b^ci;
//assign co = (a&b)|ci&(a|b);
ad01d1  u00(.s(s[ 0]), .co(co[ 0]), .a(a[ 0]), .b(b[ 0]), .ci(ci[ 0]));
ad01d1  u01(.s(s[ 1]), .co(co[ 1]), .a(a[ 1]), .b(b[ 1]), .ci(ci[ 1]));
ad01d1  u02(.s(s[ 2]), .co(co[ 2]), .a(a[ 2]), .b(b[ 2]), .ci(ci[ 2]));
ad01d1  u03(.s(s[ 3]), .co(co[ 3]), .a(a[ 3]), .b(b[ 3]), .ci(ci[ 3]));
ad01d1  u04(.s(s[ 4]), .co(co[ 4]), .a(a[ 4]), .b(b[ 4]), .ci(ci[ 4]));
ad01d1  u05(.s(s[ 5]), .co(co[ 5]), .a(a[ 5]), .b(b[ 5]), .ci(ci[ 5]));
ad01d1  u06(.s(s[ 6]), .co(co[ 6]), .a(a[ 6]), .b(b[ 6]), .ci(ci[ 6]));
ad01d1  u07(.s(s[ 7]), .co(co[ 7]), .a(a[ 7]), .b(b[ 7]), .ci(ci[ 7]));
ad01d1  u08(.s(s[ 8]), .co(co[ 8]), .a(a[ 8]), .b(b[ 8]), .ci(ci[ 8]));
ad01d1  u09(.s(s[ 9]), .co(co[ 9]), .a(a[ 9]), .b(b[ 9]), .ci(ci[ 9]));
ad01d1  u10(.s(s[10]), .co(co[10]), .a(a[10]), .b(b[10]), .ci(ci[10]));
ad01d1  u11(.s(s[11]), .co(co[11]), .a(a[11]), .b(b[11]), .ci(ci[11]));
ad01d1  u12(.s(s[12]), .co(co[12]), .a(a[12]), .b(b[12]), .ci(ci[12]));
ad01d1  u13(.s(s[13]), .co(co[13]), .a(a[13]), .b(b[13]), .ci(ci[13]));
ad01d1  u14(.s(s[14]), .co(co[14]), .a(a[14]), .b(b[14]), .ci(ci[14]));
ad01d1  u15(.s(s[15]), .co(co[15]), .a(a[15]), .b(b[15]), .ci(ci[15]));
ad01d1  u16(.s(s[16]), .co(co[16]), .a(a[16]), .b(b[16]), .ci(ci[16]));
ad01d1  u17(.s(s[17]), .co(co[17]), .a(a[17]), .b(b[17]), .ci(ci[17]));
endmodule

module vmult_csa19 (co, s, a, b, ci);
parameter width = 19;
input  [width-1:0] a, b, ci;
output [width-1:0] co, s;

//assign s = a^b^ci;
//assign co = (a&b)|ci&(a|b);
ad01d1  u00(.s(s[ 0]), .co(co[ 0]), .a(a[ 0]), .b(b[ 0]), .ci(ci[ 0]));
ad01d1  u01(.s(s[ 1]), .co(co[ 1]), .a(a[ 1]), .b(b[ 1]), .ci(ci[ 1]));
ad01d1  u02(.s(s[ 2]), .co(co[ 2]), .a(a[ 2]), .b(b[ 2]), .ci(ci[ 2]));
ad01d1  u03(.s(s[ 3]), .co(co[ 3]), .a(a[ 3]), .b(b[ 3]), .ci(ci[ 3]));
ad01d1  u04(.s(s[ 4]), .co(co[ 4]), .a(a[ 4]), .b(b[ 4]), .ci(ci[ 4]));
ad01d1  u05(.s(s[ 5]), .co(co[ 5]), .a(a[ 5]), .b(b[ 5]), .ci(ci[ 5]));
ad01d1  u06(.s(s[ 6]), .co(co[ 6]), .a(a[ 6]), .b(b[ 6]), .ci(ci[ 6]));
ad01d1  u07(.s(s[ 7]), .co(co[ 7]), .a(a[ 7]), .b(b[ 7]), .ci(ci[ 7]));
ad01d1  u08(.s(s[ 8]), .co(co[ 8]), .a(a[ 8]), .b(b[ 8]), .ci(ci[ 8]));
ad01d1  u09(.s(s[ 9]), .co(co[ 9]), .a(a[ 9]), .b(b[ 9]), .ci(ci[ 9]));
ad01d1  u10(.s(s[10]), .co(co[10]), .a(a[10]), .b(b[10]), .ci(ci[10]));
ad01d1  u11(.s(s[11]), .co(co[11]), .a(a[11]), .b(b[11]), .ci(ci[11]));
ad01d1  u12(.s(s[12]), .co(co[12]), .a(a[12]), .b(b[12]), .ci(ci[12]));
ad01d1  u13(.s(s[13]), .co(co[13]), .a(a[13]), .b(b[13]), .ci(ci[13]));
ad01d1  u14(.s(s[14]), .co(co[14]), .a(a[14]), .b(b[14]), .ci(ci[14]));
ad01d1  u15(.s(s[15]), .co(co[15]), .a(a[15]), .b(b[15]), .ci(ci[15]));
ad01d1  u16(.s(s[16]), .co(co[16]), .a(a[16]), .b(b[16]), .ci(ci[16]));
ad01d1  u17(.s(s[17]), .co(co[17]), .a(a[17]), .b(b[17]), .ci(ci[17]));
ad01d1  u18(.s(s[18]), .co(co[18]), .a(a[18]), .b(b[18]), .ci(ci[18]));
endmodule

module vmult_csa20 (co, s, a, b, ci);
parameter width = 20;
input  [width-1:0] a, b, ci;
output [width-1:0] co, s;

//assign s = a^b^ci;
//assign co = (a&b)|ci&(a|b);
ad01d1  u00(.s(s[ 0]), .co(co[ 0]), .a(a[ 0]), .b(b[ 0]), .ci(ci[ 0]));
ad01d1  u01(.s(s[ 1]), .co(co[ 1]), .a(a[ 1]), .b(b[ 1]), .ci(ci[ 1]));
ad01d1  u02(.s(s[ 2]), .co(co[ 2]), .a(a[ 2]), .b(b[ 2]), .ci(ci[ 2]));
ad01d1  u03(.s(s[ 3]), .co(co[ 3]), .a(a[ 3]), .b(b[ 3]), .ci(ci[ 3]));
ad01d1  u04(.s(s[ 4]), .co(co[ 4]), .a(a[ 4]), .b(b[ 4]), .ci(ci[ 4]));
ad01d1  u05(.s(s[ 5]), .co(co[ 5]), .a(a[ 5]), .b(b[ 5]), .ci(ci[ 5]));
ad01d1  u06(.s(s[ 6]), .co(co[ 6]), .a(a[ 6]), .b(b[ 6]), .ci(ci[ 6]));
ad01d1  u07(.s(s[ 7]), .co(co[ 7]), .a(a[ 7]), .b(b[ 7]), .ci(ci[ 7]));
ad01d1  u08(.s(s[ 8]), .co(co[ 8]), .a(a[ 8]), .b(b[ 8]), .ci(ci[ 8]));
ad01d1  u09(.s(s[ 9]), .co(co[ 9]), .a(a[ 9]), .b(b[ 9]), .ci(ci[ 9]));
ad01d1  u10(.s(s[10]), .co(co[10]), .a(a[10]), .b(b[10]), .ci(ci[10]));
ad01d1  u11(.s(s[11]), .co(co[11]), .a(a[11]), .b(b[11]), .ci(ci[11]));
ad01d1  u12(.s(s[12]), .co(co[12]), .a(a[12]), .b(b[12]), .ci(ci[12]));
ad01d1  u13(.s(s[13]), .co(co[13]), .a(a[13]), .b(b[13]), .ci(ci[13]));
ad01d1  u14(.s(s[14]), .co(co[14]), .a(a[14]), .b(b[14]), .ci(ci[14]));
ad01d1  u15(.s(s[15]), .co(co[15]), .a(a[15]), .b(b[15]), .ci(ci[15]));
ad01d1  u16(.s(s[16]), .co(co[16]), .a(a[16]), .b(b[16]), .ci(ci[16]));
ad01d1  u17(.s(s[17]), .co(co[17]), .a(a[17]), .b(b[17]), .ci(ci[17]));
ad01d1  u18(.s(s[18]), .co(co[18]), .a(a[18]), .b(b[18]), .ci(ci[18]));
ad01d1  u19(.s(s[19]), .co(co[19]), .a(a[19]), .b(b[19]), .ci(ci[19]));
endmodule

module vmult_csa22 (co, s, a, b, ci);
parameter width = 22;
input  [width-1:0] a, b, ci;
output [width-1:0] co, s;

//assign s = a^b^ci;
//assign co = (a&b)|ci&(a|b);
ad01d1  u00(.s(s[ 0]), .co(co[ 0]), .a(a[ 0]), .b(b[ 0]), .ci(ci[ 0]));
ad01d1  u01(.s(s[ 1]), .co(co[ 1]), .a(a[ 1]), .b(b[ 1]), .ci(ci[ 1]));
ad01d1  u02(.s(s[ 2]), .co(co[ 2]), .a(a[ 2]), .b(b[ 2]), .ci(ci[ 2]));
ad01d1  u03(.s(s[ 3]), .co(co[ 3]), .a(a[ 3]), .b(b[ 3]), .ci(ci[ 3]));
ad01d1  u04(.s(s[ 4]), .co(co[ 4]), .a(a[ 4]), .b(b[ 4]), .ci(ci[ 4]));
ad01d1  u05(.s(s[ 5]), .co(co[ 5]), .a(a[ 5]), .b(b[ 5]), .ci(ci[ 5]));
ad01d1  u06(.s(s[ 6]), .co(co[ 6]), .a(a[ 6]), .b(b[ 6]), .ci(ci[ 6]));
ad01d1  u07(.s(s[ 7]), .co(co[ 7]), .a(a[ 7]), .b(b[ 7]), .ci(ci[ 7]));
ad01d1  u08(.s(s[ 8]), .co(co[ 8]), .a(a[ 8]), .b(b[ 8]), .ci(ci[ 8]));
ad01d1  u09(.s(s[ 9]), .co(co[ 9]), .a(a[ 9]), .b(b[ 9]), .ci(ci[ 9]));
ad01d1  u10(.s(s[10]), .co(co[10]), .a(a[10]), .b(b[10]), .ci(ci[10]));
ad01d1  u11(.s(s[11]), .co(co[11]), .a(a[11]), .b(b[11]), .ci(ci[11]));
ad01d1  u12(.s(s[12]), .co(co[12]), .a(a[12]), .b(b[12]), .ci(ci[12]));
ad01d1  u13(.s(s[13]), .co(co[13]), .a(a[13]), .b(b[13]), .ci(ci[13]));
ad01d1  u14(.s(s[14]), .co(co[14]), .a(a[14]), .b(b[14]), .ci(ci[14]));
ad01d1  u15(.s(s[15]), .co(co[15]), .a(a[15]), .b(b[15]), .ci(ci[15]));
ad01d1  u16(.s(s[16]), .co(co[16]), .a(a[16]), .b(b[16]), .ci(ci[16]));
ad01d1  u17(.s(s[17]), .co(co[17]), .a(a[17]), .b(b[17]), .ci(ci[17]));
ad01d1  u18(.s(s[18]), .co(co[18]), .a(a[18]), .b(b[18]), .ci(ci[18]));
ad01d1  u19(.s(s[19]), .co(co[19]), .a(a[19]), .b(b[19]), .ci(ci[19]));
ad01d1  u20(.s(s[20]), .co(co[20]), .a(a[20]), .b(b[20]), .ci(ci[20]));
ad01d1  u21(.s(s[21]), .co(co[21]), .a(a[21]), .b(b[21]), .ci(ci[21]));
endmodule

module vmult_csa24 (co, s, a, b, ci);
parameter width = 24;
input  [width-1:0] a, b, ci;
output [width-1:0] co, s;

//assign s = a^b^ci;
//assign co = (a&b)|ci&(a|b);
ad01d1  u00(.s(s[ 0]), .co(co[ 0]), .a(a[ 0]), .b(b[ 0]), .ci(ci[ 0]));
ad01d1  u01(.s(s[ 1]), .co(co[ 1]), .a(a[ 1]), .b(b[ 1]), .ci(ci[ 1]));
ad01d1  u02(.s(s[ 2]), .co(co[ 2]), .a(a[ 2]), .b(b[ 2]), .ci(ci[ 2]));
ad01d1  u03(.s(s[ 3]), .co(co[ 3]), .a(a[ 3]), .b(b[ 3]), .ci(ci[ 3]));
ad01d1  u04(.s(s[ 4]), .co(co[ 4]), .a(a[ 4]), .b(b[ 4]), .ci(ci[ 4]));
ad01d1  u05(.s(s[ 5]), .co(co[ 5]), .a(a[ 5]), .b(b[ 5]), .ci(ci[ 5]));
ad01d1  u06(.s(s[ 6]), .co(co[ 6]), .a(a[ 6]), .b(b[ 6]), .ci(ci[ 6]));
ad01d1  u07(.s(s[ 7]), .co(co[ 7]), .a(a[ 7]), .b(b[ 7]), .ci(ci[ 7]));
ad01d1  u08(.s(s[ 8]), .co(co[ 8]), .a(a[ 8]), .b(b[ 8]), .ci(ci[ 8]));
ad01d1  u09(.s(s[ 9]), .co(co[ 9]), .a(a[ 9]), .b(b[ 9]), .ci(ci[ 9]));
ad01d1  u10(.s(s[10]), .co(co[10]), .a(a[10]), .b(b[10]), .ci(ci[10]));
ad01d1  u11(.s(s[11]), .co(co[11]), .a(a[11]), .b(b[11]), .ci(ci[11]));
ad01d1  u12(.s(s[12]), .co(co[12]), .a(a[12]), .b(b[12]), .ci(ci[12]));
ad01d1  u13(.s(s[13]), .co(co[13]), .a(a[13]), .b(b[13]), .ci(ci[13]));
ad01d1  u14(.s(s[14]), .co(co[14]), .a(a[14]), .b(b[14]), .ci(ci[14]));
ad01d1  u15(.s(s[15]), .co(co[15]), .a(a[15]), .b(b[15]), .ci(ci[15]));
ad01d1  u16(.s(s[16]), .co(co[16]), .a(a[16]), .b(b[16]), .ci(ci[16]));
ad01d1  u17(.s(s[17]), .co(co[17]), .a(a[17]), .b(b[17]), .ci(ci[17]));
ad01d1  u18(.s(s[18]), .co(co[18]), .a(a[18]), .b(b[18]), .ci(ci[18]));
ad01d1  u19(.s(s[19]), .co(co[19]), .a(a[19]), .b(b[19]), .ci(ci[19]));
ad01d1  u20(.s(s[20]), .co(co[20]), .a(a[20]), .b(b[20]), .ci(ci[20]));
ad01d1  u21(.s(s[21]), .co(co[21]), .a(a[21]), .b(b[21]), .ci(ci[21]));
ad01d1  u22(.s(s[22]), .co(co[22]), .a(a[22]), .b(b[22]), .ci(ci[22]));
ad01d1  u23(.s(s[23]), .co(co[23]), .a(a[23]), .b(b[23]), .ci(ci[23]));
endmodule

module vmult_ha(co, s, a, b);
input a,b;
output co, s;

//assign s = a^b;
//assign co = (a&b);
an02d1 u0(.z(co), .a1(a), .a2(b));
xo02d1 u1(.z(s),  .a1(a), .a2(b));

endmodule
/*****************************
 *
 *****************************/
module vmult_cla (a, b, clk, coh,col);

input [24:0] a;
input [24:0] b;
input clk;

output coh,col;

wire co_l;

wire [30:6] c0b;
wire [30:7] c1b;

// conditional cells:
nd02d2 c06  (.a1(a[0]),  .a2(b[0]),  .zn(c0b[6]));

nd02d2 c07  (.a1(a[1]),  .a2(b[1]),  .zn(c0b[7]));
nr02d2 c17  (.a1(a[1]),  .a2(b[1]),  .zn(c1b[7]));

nd02d2 c08  (.a1(a[2]),  .a2(b[2]),  .zn(c0b[8]));
nr02d2 c18  (.a1(a[2]),  .a2(b[2]),  .zn(c1b[8]));

nd02d2 c09  (.a1(a[3]),  .a2(b[3]),  .zn(c0b[9]));
nr02d2 c19  (.a1(a[3]),  .a2(b[3]),  .zn(c1b[9]));

nd02d2 c010 (.a1(a[4]),  .a2(b[4]),  .zn(c0b[10]));
nr02d2 c110 (.a1(a[4]),  .a2(b[4]),  .zn(c1b[10]));

nd02d2 c011 (.a1(a[5]),  .a2(b[5]),  .zn(c0b[11]));
nr02d2 c111 (.a1(a[5]),  .a2(b[5]),  .zn(c1b[11]));

nd02d2 c012 (.a1(a[6]),  .a2(b[6]),  .zn(c0b[12]));
nr02d2 c112 (.a1(a[6]),  .a2(b[6]),  .zn(c1b[12]));

nd02d2 c013 (.a1(a[7]),  .a2(b[7]),  .zn(c0b[13]));
nr02d2 c113 (.a1(a[7]),  .a2(b[7]),  .zn(c1b[13]));

nd02d2 c014 (.a1(a[8]),  .a2(b[8]),  .zn(c0b[14]));
nr02d2 c114 (.a1(a[8]),  .a2(b[8]),  .zn(c1b[14]));

nd02d2 c015 (.a1(a[9]),  .a2(b[9]),  .zn(c0b[15]));
nr02d2 c115 (.a1(a[9]),  .a2(b[9]),  .zn(c1b[15]));

nd02d2 c016 (.a1(a[10]), .a2(b[10]), .zn(c0b[16]));
nr02d2 c116 (.a1(a[10]), .a2(b[10]), .zn(c1b[16]));

nd02d2 c017 (.a1(a[11]), .a2(b[11]), .zn(c0b[17]));
nr02d2 c117 (.a1(a[11]), .a2(b[11]), .zn(c1b[17]));

nd02d2 c018 (.a1(a[12]), .a2(b[12]), .zn(c0b[18]));
nr02d2 c118 (.a1(a[12]), .a2(b[12]), .zn(c1b[18]));

nd02d2 c019 (.a1(a[13]), .a2(b[13]), .zn(c0b[19]));
nr02d2 c119 (.a1(a[13]), .a2(b[13]), .zn(c1b[19]));

nd02d2 c020 (.a1(a[14]), .a2(b[14]), .zn(c0b[20]));
nr02d2 c120 (.a1(a[14]), .a2(b[14]), .zn(c1b[20]));

nd02d2 c021 (.a1(a[15]), .a2(b[15]), .zn(c0b[21]));
nr02d2 c121 (.a1(a[15]), .a2(b[15]), .zn(c1b[21]));

nd02d2 c022 (.a1(a[16]), .a2(b[16]), .zn(c0b[22]));
nr02d2 c122 (.a1(a[16]), .a2(b[16]), .zn(c1b[22]));

nd02d2 c023 (.a1(a[17]), .a2(b[17]), .zn(c0b[23]));
nr02d2 c123 (.a1(a[17]), .a2(b[17]), .zn(c1b[23]));

nd02d2 c024 (.a1(a[18]), .a2(b[18]), .zn(c0b[24]));
nr02d2 c124 (.a1(a[18]), .a2(b[18]), .zn(c1b[24]));

nd02d2 c025 (.a1(a[19]), .a2(b[19]), .zn(c0b[25]));
nr02d2 c125 (.a1(a[19]), .a2(b[19]), .zn(c1b[25]));

nd02d2 c026 (.a1(a[20]), .a2(b[20]), .zn(c0b[26]));
nr02d2 c126 (.a1(a[20]), .a2(b[20]), .zn(c1b[26]));

nd02d2 c027 (.a1(a[21]), .a2(b[21]), .zn(c0b[27]));
nr02d2 c127 (.a1(a[21]), .a2(b[21]), .zn(c1b[27]));

nd02d2 c028 (.a1(a[22]), .a2(b[22]), .zn(c0b[28]));
nr02d2 c128 (.a1(a[22]), .a2(b[22]), .zn(c1b[28]));

nd02d2 c029 (.a1(a[23]), .a2(b[23]), .zn(c0b[29]));
nr02d2 c129 (.a1(a[23]), .a2(b[23]), .zn(c1b[29]));

nd02d2 c030 (.a1(a[24]), .a2(b[24]), .zn(c0b[30]));
nr02d2 c130 (.a1(a[24]), .a2(b[24]), .zn(c1b[30]));

// first rank of muxes (all muxes before register should be high performance):
mx21d1h mac08  (.s(c0b[7]),  .i1(c0b[8]),  .i0(c1b[8]),  .z(mac0b8));
mx21d1h mac18  (.s(c1b[7]),  .i1(c0b[8]),  .i0(c1b[8]),  .z(mac1b8));

mx21d1h mac010 (.s(c0b[9]),  .i1(c0b[10]), .i0(c1b[10]), .z(mac0b10));
mx21d1h mac110 (.s(c1b[9]),  .i1(c0b[10]), .i0(c1b[10]), .z(mac1b10));

mx21d1h mac012 (.s(c0b[11]), .i1(c0b[12]), .i0(c1b[12]), .z(mac0b12));
mx21d1h mac112 (.s(c1b[11]), .i1(c0b[12]), .i0(c1b[12]), .z(mac1b12));

mx21d1h mac014 (.s(c0b[13]), .i1(c0b[14]), .i0(c1b[14]), .z(mac0b14));
mx21d1h mac114 (.s(c1b[13]), .i1(c0b[14]), .i0(c1b[14]), .z(mac1b14));

mx21d1h mac016 (.s(c0b[15]), .i1(c0b[16]), .i0(c1b[16]), .z(mac0b16));
mx21d1h mac116 (.s(c1b[15]), .i1(c0b[16]), .i0(c1b[16]), .z(mac1b16));

mx21d1h mac018 (.s(c0b[17]), .i1(c0b[18]), .i0(c1b[18]), .z(mac0b18));
mx21d1h mac118 (.s(c1b[17]), .i1(c0b[18]), .i0(c1b[18]), .z(mac1b18));

mx21d1h mac020 (.s(c0b[19]), .i1(c0b[20]), .i0(c1b[20]), .z(mac0b20));
mx21d1h mac120 (.s(c1b[19]), .i1(c0b[20]), .i0(c1b[20]), .z(mac1b20));

mx21d1h mac022 (.s(c0b[21]), .i1(c0b[22]), .i0(c1b[22]), .z(mac0b22));
mx21d1h mac122 (.s(c1b[21]), .i1(c0b[22]), .i0(c1b[22]), .z(mac1b22));

mx21d1h mac024 (.s(c0b[23]), .i1(c0b[24]), .i0(c1b[24]), .z(mac0b24));
mx21d1h mac124 (.s(c1b[23]), .i1(c0b[24]), .i0(c1b[24]), .z(mac1b24));

mx21d1h mac026 (.s(c0b[25]), .i1(c0b[26]), .i0(c1b[26]), .z(mac0b26));
mx21d1h mac126 (.s(c1b[25]), .i1(c0b[26]), .i0(c1b[26]), .z(mac1b26));

mx21d1h mac028 (.s(c0b[27]), .i1(c0b[28]), .i0(c1b[28]), .z(mac0b28));
mx21d1h mac128 (.s(c1b[27]), .i1(c0b[28]), .i0(c1b[28]), .z(mac1b28));

mx21d1h mac030 (.s(c0b[29]), .i1(c0b[30]), .i0(c1b[30]), .z(mac0b30));
mx21d1h mac130 (.s(c1b[29]), .i1(c0b[30]), .i0(c1b[30]), .z(mac1b30));

// second rank of muxes:
mx21d1h mbc010 (.s(mac0b8),  .i1(mac0b10), .i0(mac1b10), .z(mbc0b10));
mx21d1h mbc110 (.s(mac1b8),  .i1(mac0b10), .i0(mac1b10), .z(mbc1b10));

mx21d1h mbc014 (.s(mac0b12), .i1(mac0b14), .i0(mac1b14), .z(mbc0b14));
mx21d1h mbc114 (.s(mac1b12), .i1(mac0b14), .i0(mac1b14), .z(mbc1b14));

mx21d1h mbc018 (.s(mac0b16), .i1(mac0b18), .i0(mac1b18), .z(mbc0b18));
mx21d1h mbc118 (.s(mac1b16), .i1(mac0b18), .i0(mac1b18), .z(mbc1b18));

mx21d1h mbc022 (.s(mac0b20), .i1(mac0b22), .i0(mac1b22), .z(mbc0b22));
mx21d1h mbc122 (.s(mac1b20), .i1(mac0b22), .i0(mac1b22), .z(mbc1b22));

mx21d1h mbc026 (.s(mac0b24), .i1(mac0b26), .i0(mac1b26), .z(mbc0b26));
mx21d1h mbc126 (.s(mac1b24), .i1(mac0b26), .i0(mac1b26), .z(mbc1b26));

mx21d1h mbc030 (.s(mac0b28), .i1(mac0b30), .i0(mac1b30), .z(mbc0b30));
mx21d1h mbc130 (.s(mac1b28), .i1(mac0b30), .i0(mac1b30), .z(mbc1b30));

// third rank of muxes:
//mx21d1h mcc014 (.s(mbc0b10), .i1(mbc0b14), .i0(mbc1b14), .z(mcc0b14_p));
//mx21d1h mcc114 (.s(mbc1b10), .i1(mbc0b14), .i0(mbc1b14), .z(mcc1b14_p));
//
//mx21d1h mcc022 (.s(mbc0b18), .i1(mbc0b22), .i0(mbc1b22), .z(mcc0b22_p));
//mx21d1h mcc122 (.s(mbc1b18), .i1(mbc0b22), .i0(mbc1b22), .z(mcc1b22_p));
//
//mx21d1h mcc030 (.s(mbc0b26), .i1(mbc0b30), .i0(mbc1b30), .z(mcc0b30_p));
//mx21d1h mcc130 (.s(mbc1b26), .i1(mbc0b30), .i0(mbc1b30), .z(mcc1b30_p));

mfntnb dff_mcc014 (.sa(mbc0b10), .da(mbc0b14), .db(mbc1b14), .q(mcc0b14), .cp(clk));
mfntnb dff_mcc114 (.sa(mbc1b10), .da(mbc0b14), .db(mbc1b14), .q(mcc1b14), .cp(clk));

mfntnb dff_mcc022 (.sa(mbc0b18), .da(mbc0b22), .db(mbc1b22), .q(mcc0b22), .cp(clk));
mfntnb dff_mcc122 (.sa(mbc1b18), .da(mbc0b22), .db(mbc1b22), .q(mcc1b22), .cp(clk));

mfntnb dff_mcc030 (.sa(mbc0b26), .da(mbc0b30), .db(mbc1b30), .q(mcc0b30), .cp(clk));
mfntnb dff_mcc130 (.sa(mbc1b26), .da(mbc0b30), .db(mbc1b30), .q(mcc1b30), .cp(clk));

dfntnb dff_7(.q(c0b_d), .d(c0b[6]), .cp(clk));

// fourth rank of muxes:
mx21d1 mdc014 (.s(c0b_d),  .i1(mcc0b14), .i0(mcc1b14), .z(mdc0b14));

mx21d1 mdc030 (.s(mcc0b22), .i1(mcc0b30), .i0(mcc1b30), .z(mdc0b30));
mx21d1 mdc130 (.s(mcc1b22), .i1(mcc0b30), .i0(mcc1b30), .z(mdc1b30));

// fifth rank of muxes:
mx21d1 mec030 (.s(mdc0b14), .i1(mdc0b30), .i0(mdc1b30), .z(co_l));

in01d2  inv_h(.zn(coh), .i(co_l));
in01d2  inv_l(.zn(col), .i(mdc0b14));

endmodule // vmult_cla