vopcodes.h
2.63 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
/*
*************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************
*/
// $Id: vopcodes.h,v 1.1 2002/03/28 00:26:14 berndt Exp $
/*
* These are the RSP VU operate instructions, which follow the general
* organization of a MIPS coprocessor, with instructions mapped into CP2.
*
* If the opcode of the instructon is COP2 and bit 25 of the instruction
* is set, then it is a VU operate and we pass this instruction to the VU for
* further decoding and execution.
*
* The lower 6 bits of the instruction will hold the VU opcode, which
* are listed below:
*
*
* multiply instructions:
* opcode bits: 00 a fff
* where 00 is the mult op, a is accumulator or not,
* and fff is the format.
*
*/
`define VMULF 'h00
`define VMACF 'h08
`define VMULU 'h01
`define VMACU 'h09
`define VRNDP 'h02
`define VRNDN 'h0a
`define VMULQ 'h03
`define VMACQ 'h0b
`define VMUDL 'h04
`define VMADL 'h0c
`define VMUDM 'h05
`define VMADM 'h0d
`define VMUDN 'h06
`define VMADN 'h0e
`define VMUDH 'h07
`define VMADH 'h0f
/* add instructions: */
`define VADD 'h10
`define VSUB 'h11
// `define VSUT 'h12
`define VABS 'h13
`define VADDC 'h14
`define VSUBC 'h15
// `define VADDB 'h16
// `define VSUBB 'h17
// `define VACCB 'h18
// `define VSUCB 'h19
// `define VSAD 'h1a
// `define VSAC 'h1b
// `define VSUM 'h1c
`define VSAR 'h1d
/* select instructions: */
`define VLT 'h20
`define VEQ 'h21
`define VNE 'h22
`define VGE 'h23
`define VCL 'h24
`define VCH 'h25
`define VCR 'h26
`define VMRG 'h27
/* logical instructions: */
`define VAND 'h28
`define VNAND 'h29
`define VOR 'h2a
`define VNOR 'h2b
`define VXOR 'h2c
`define VXNOR 'h2d
/* divide instructions: */
/* opcode bits: 110 f tt */
/* where 110 is the div op, f is the function */
/* (reciprocal or reciprocal squared), and tt is the */
/* type, single/double high/low */
`define VRCP 'h30
`define VRCPL 'h31
`define VRCPH 'h32
`define VRSQ 'h34
`define VRSQL 'h35
`define VRSQH 'h36
`define VMOV 'h33
/* pack instructions: */
/* bit 2 is pack/unpack */
// `define VINST 'h3c
// `define VEXTT 'h38
// `define VINSQ 'h3d
// `define VEXTQ 'h39
// `define VINSN 'h3e
// `define VEXTN 'h3a