audio_tasks.v
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task ai_test;
// audio test debug socket
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// put some data in the dram first
write_word(BUS_ADDRESS_DRAM, 3, 32'h0ad00da0);
write_word(BUS_ADDRESS_DRAM+4, 3, 32'h1ad11da1);
write_word(BUS_ADDRESS_DRAM+8, 3, 32'h2ad22da2);
write_word(BUS_ADDRESS_DRAM+12, 3, 32'h3ad33da3);
write_word(BUS_ADDRESS_DRAM+16, 3, 32'h4ad44da4);
write_word(BUS_ADDRESS_DRAM+20, 3, 32'h5ad55da5);
write_word(BUS_ADDRESS_DRAM+24, 3, 32'h6ad66da6);
write_word(BUS_ADDRESS_DRAM+28, 3, 32'h7ad77da7);
write_word(BUS_ADDRESS_DRAM+32, 3, 32'h8ad88da8);
// protocol is:
// set bit 0 of control reg
// write address
// write length
// loop_forever {
// write address
// write length
// while (bit_31_of_status == 1) wait;
// }
// need set video control reg ctrl[5] vbus_clk_en_l
write_word(BUS_ADDRESS_VI_CTRL, 3, 0); // external video clock
//write_word(BUS_ADDRESS_VI_CTRL, 3, 5'b10000); // video clock = sys clock
// initialize
// set a dac rate 13:0
write_word(BUS_ADDRESS_AI_DACRATE, 3, 131);
// set bit rate 3:0
write_word(BUS_ADDRESS_AI_BITRATE, 3, 1);
// setting control bit 0 to 1 sets dma_enable
write_word(BUS_ADDRESS_AI_CONTROL, 3, 1);
write_word(BUS_ADDRESS_AI_DRAM_ADDRESS, 3, 8);
// length reg is 18 bits, 8byte aligned w/r max length is h3fff8
write_word(BUS_ADDRESS_AI_LENGTH, 3, 64);
read_word(BUS_ADDRESS_AI_STATUS, 3);
while ((data[0] && 32'h40000000) == 1) begin
$display (" Read of ai status %h ",data[0]);
read_word(BUS_ADDRESS_AI_DRAM_ADDRESS, 3);
$display (" Read of ai dram_address %h ",data[0]);
read_word(BUS_ADDRESS_AI_LENGTH, 3);
$display (" Read of ai length %h ",data[0]);
read_word(BUS_ADDRESS_AI_STATUS, 3);
end
// wait for a while and watch dma
repeat (200) @(posedge clock);
$finish;
end
endtask