// channel_monitor.v - module to monitor channel activity
//
// Copyright 1994, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
// 
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
// 
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.
//
// This module looks at channel activity, parses requests and outputs
// useful data to log file. Since BusEnable must precede a request, the module
// waits for the first assertion of BusEnable to start monitoring the channel.
//
// Usage: channel_monitor #("channel.log",1,0) channel1(
//     		SOut,		// SIn
//		SIn,		// SOut
//		BusClk,		// BusClk
//		BusEnable,	// BusEnable	
//		BusCtrl,	// BusCtrl
//		BusData,	// BusData[8:0]
//		Section);	// ravs section number
//
// first optional parameter is logfile name. if none specified, output is sent
//   to stdout and default logfile.
// second optional parameter is channel number. if none specified, default is 0.
// third optional parameter is offset for comments for this channel in
//   the log file. default is 0.
// required ports are the pins of the channel to be monitored
//
// 1. MON_CHANNEL define required to enable channel monitor module
// 2. RDRAM4M define tells channel monitor to use 4M delay register settings,
//    else uses 16M delay register settings.
//
// Note, if channel_monitor is used to monitor multiple channels, the logfile names
// used by the different instantiations must be different or the last one to
// perform an $fopen will prevail, closing all subsequent open log files.
// 
// Specifying +SUPPRESS_CHANNEL on command line will disable almost all the
// log file output. Useful during long runs to minimize log file size.
//
//Revision 1.16  1994/10/24  23:26:53  harlan
//SUPPRESS_CHANNEL will suppress decode of request packet to log file.
//
//Revision 1.15  1994/10/02  04:33:04  harlan
//No change.
//
//Revision 1.14  1994/09/23  01:20:53  harlan
//Command line argument +SUPPRESS_CHANNEL will suppress display of
//channel value every buscycle, greatly reducing log file output.
//
//Revision 1.13  1994/09/22  22:26:23  harlan
//Display section number when decode requests.
//
//Revision 1.12  1994/09/22  16:28:13  harlan
//Decrease idlecount so less log file output
//
//Revision 1.11  1994/09/16  17:05:40  harlan
//Change quickstart values for ackwindelay, readdelay and writedelay.
//
//Revision 1.10  1994/09/09  22:05:47  harlan
//Remove buscycle number from log file output.
//
//Revision 1.9  1994/09/07  00:04:35  harlan
//Add stuff to disable log file output while channel is idle for
//long periods of time.
//
//Revision 1.8  1994/09/02  00:57:37  harlan
//Change initial delay values to quickstart values in rdram_near_model.v.
//
//Revision 1.7  1994/07/27  22:36:24  harlan
//Change all pins to inputs only.
//Fix part select error in unpack task.
//
//Revision 1.6  1994/07/26  20:07:10  harlan
//Change so starts monitor on BusEnable low level rather than negedge
//of BusEnable. Was getting false trigger when BusEnable went from 1 to x.
//
//Revision 1.5  1994/07/22  22:30:13  harlan
//Change %5.0f to %6.0f for compatibility.
//
//Revision 1.4  1994/07/05  22:56:11  harlan
//Make logfile output more meaningful in default case.
//
//Revision 1.3  1994/06/30  23:59:22  harlan
//Add timescale directive.
//
//Revision 1.2  1994/06/30  19:39:04  harlan
//Change name from monitor_channel to channel_monitor.
//
//Revision 1.1  1994/06/30  18:37:07  harlan
//Initial revision
//

// This define can go anywhere and does not have to be in this module.
// MON_CHANNEL can also be defined on the command line in the GNUmakefile.
`define MON_CHANNEL

`ifdef MON_CHANNEL		// check if want to enable channel monitor

// ****************************************************************************
// channel monitor
// ****************************************************************************

`timescale 1ns/1ns

module channel_monitor(
    SIn,
    SOut,
    BusClk,
    BusEnable,
    BusCtrl,
    BusData,
    Section
    );
// optional parameters
parameter logfile = "";		// send output to this logfile

parameter C_NO = 0;		// number of this channel - used for multiple rdrams
				// so identificable in log file
parameter offset = 0;		// offset of comments in log file	

// required pins. since this is monitor these pins are all inputs
input		SIn;
input		SOut;
input		BusClk;
input		BusEnable;
input		BusCtrl;
input [8:0]	BusData;
input [31:0]	Section;



// declarations
integer		BusCycleCnt;
integer		ReqPacketCnt;
reg		FoundRequest;
integer		PacketCnt;
integer		EnableRequestCnt;	
integer		AckPacketCnt;
integer		WritePacketCnt;
integer		ReadPacketCnt;
integer		SerialAddressCnt;
integer		WritePacketByte;
integer		octbyte;
integer		AckWinDelay;	// current value of this delay
integer		ReadDelay;	// current value of this delay
integer		AckDelay;	// current value of this delay
integer		WriteDelay;	// current value of this delay
integer		log;		// descriptor for channel_logfile

reg [40*8:1]	text;
reg [40*8:1]	optype;
reg [60*8:1]	pad;
reg [100*8:0]	align;
reg [5:0] 	opcode;
      	      	// Request packet
reg [9:0]	ReqPacket0,ReqPacket1,ReqPacket2,ReqPacket3,ReqPacket4,ReqPacket5;
      	      	// Ack packet
reg		AckPacket0,AckPacket1;		
      	      	// First Write Packet
reg [8:0]	WritePacket0,WritePacket1,WritePacket2,WritePacket3,
      	      	WritePacket4,WritePacket5,WritePacket6,WritePacket7;
reg [35:0]	Adr,AdrS,AdrR;
reg [8:0]	AddressSelect;
reg		WregDeviceId,WregDelay,WregMode,WregRefInterval,WregRefRow,
      	      	WregAddressSelect;
reg [14:0]	DeviceId;
reg		displayon;	// =1 write log file, =0 dont write log file
integer		idlecount;	// idle channel cycles

// request packets opcodes {Op[3:0],OpX[1:0]}
// used to decode opcodes
parameter	RseqOp			= 6'b000000;
parameter	RnsqOp			= 6'b000001;

parameter	RseqAltOp		= 6'b000100;
parameter	RnsqAltOp		= 6'b000101;

parameter	RseqxOp			= 6'b000x00;
parameter	RnsqxOp			= 6'b000x01;

parameter	Rx1Op			= 6'b00000x; // R{seq,nsq}
parameter	Rx2Op			= 6'b00010x;
parameter	Rx3Op			= 6'b000x0x;

parameter	WseqNpbOp		= 6'b010000;
parameter	WseqDpbOp		= 6'b010001;
parameter	WseqBpbOp		= 6'b010010;
parameter	WseqMpbOp		= 6'b010011;

parameter	WseqNpbAltOp		= 6'b010100;
parameter	WseqDpbAltOp		= 6'b010101;
parameter	WseqBpbAltOp		= 6'b010110;
parameter	WseqMpbAltOp		= 6'b010111;

parameter	WseqNpbxOp		= 6'b010x00;
parameter	WseqDpbxOp		= 6'b010x01;
parameter	WseqBpbxOp		= 6'b010x10;
parameter	WseqMpbxOp		= 6'b010x11;

parameter	WseqNpbDpbx1Op		= 6'b01000x; // Npb or Dpb
parameter	WseqNpbDpbx2Op		= 6'b01010x;
parameter	WseqNpbDpbx3Op		= 6'b010x0x;
parameter	WseqNpbBpbx1Op		= 6'b0100x0; // Npb or Bpb
parameter	WseqNpbBpbx2Op		= 6'b0101x0;
parameter	WseqNpbBpbx3Op		= 6'b010xx0;
parameter	WseqBpbMpbx1Op		= 6'b01001x; // Bpb or Mpb
parameter	WseqBpbMpbx2Op		= 6'b01011x;
parameter	WseqBpbMpbx3Op		= 6'b010x1x;
parameter	WseqDpbMpbx1Op		= 6'b0100x1; // Dpb or Mpb
parameter	WseqDpbMpbx2Op		= 6'b0101x1;
parameter	WseqDpbMpbx3Op		= 6'b010xx1;
parameter	Wseqx1Op		= 6'b0100xx; // Wseq*		
parameter	Wseqx2Op		= 6'b0101xx;
parameter	Wseqx3Op		= 6'b010xxx;

parameter	RregOp			= 6'b011000;
parameter	WregOp			= 6'b011100;

parameter	WnsqNpbOp		= 6'b100000;
parameter	WnsqDpbOp		= 6'b100001;
parameter	WnsqBpbOp		= 6'b100010;
parameter	WnsqMpbOp		= 6'b100011;

parameter	WnsqNpbAltOp		= 6'b100100;
parameter	WnsqDpbAltOp		= 6'b100101;
parameter	WnsqBpbAltOp		= 6'b100110;
parameter	WnsqMpbAltOp		= 6'b100111;

parameter	WnsqNpbxOp		= 6'b100x00;
parameter	WnsqDpbxOp		= 6'b100x01;
parameter	WnsqBpbxOp		= 6'b100x10;
parameter	WnsqMpbxOp		= 6'b100x11;

parameter	WnsqNpbDpbx1Op		= 6'b10000x; // Npb or Dpb
parameter	WnsqNpbDpbx2Op		= 6'b10010x;
parameter	WnsqNpbDpbx3Op		= 6'b100x0x;
parameter	WnsqNpbBpbx1Op		= 6'b1000x0; // Npb or Bpb
parameter	WnsqNpbBpbx2Op		= 6'b1001x0;
parameter	WnsqNpbBpbx3Op		= 6'b100xx0;
parameter	WnsqBpbMpbx1Op		= 6'b10001x; // Bpb or Mpb
parameter	WnsqBpbMpbx2Op		= 6'b10011x;
parameter	WnsqBpbMpbx3Op		= 6'b100x1x;
parameter	WnsqDpbMpbx1Op		= 6'b1000x1; // Dpb or Mpb
parameter	WnsqDpbMpbx2Op		= 6'b1001x1;
parameter	WnsqDpbMpbx3Op		= 6'b100xx1;
parameter	Wnsqx1Op		= 6'b1000xx; // Wnsq*		
parameter	Wnsqx2Op		= 6'b1001xx;
parameter	Wnsqx3Op		= 6'b100xxx;

parameter	WbnsNpbOp		= 6'b110000;
parameter	WbnsDpbOp		= 6'b110001;
parameter	WbnsMpbOp		= 6'b110011;

parameter	WbnsNpbAltOp		= 6'b110100;
parameter	WbnsDpbAltOp		= 6'b110101;
parameter	WbnsMpbAltOp		= 6'b110111;

parameter	WbnsNpbxOp		= 6'b110x00;
parameter	WbnsDpbxOp		= 6'b110x01;
parameter	WbnsMpbxOp		= 6'b110x11;

parameter	Wbnsx1Op		= 6'b11000x; // Npb or Dpb
parameter	Wbnsx2Op		= 6'b11010x;
parameter	Wbnsx3Op		= 6'b110x0x;
parameter	Wbnsx4Op		= 6'b1100x1; // Dpb or Mpb
parameter	Wbnsx5Op		= 6'b1101x1;
parameter	Wbnsx6Op		= 6'b110xx1;

parameter	WregBnOp		= 6'b111000;
parameter	WregBOp			= 6'b111100;

// register address definitions (AdrS[9:2])
// used to decode register type
parameter 	adr_DeviceType 		= 8'b00000000;
parameter 	DeviceTypeReg 		= adr_DeviceType;
parameter 	adr_DeviceID 		= 8'b00000001;
parameter 	DeviceIdReg 		= adr_DeviceID;
parameter 	adr_Delay 		= 8'b00000010;
parameter 	DelayReg		= adr_Delay;
parameter 	adr_Mode 		= 8'b00000011;
parameter 	ModeReg			= adr_Mode;
parameter 	adr_RefInterval  	= 8'b00000100;
parameter 	RefIntervalReg 		= adr_RefInterval;
parameter 	adr_RefRow 		= 8'b00000101;
parameter 	RefRowReg		= adr_RefRow;
parameter 	adr_RasInterval 	= 8'b00000110;
parameter 	RasIntervalReg 		= adr_RasInterval;
parameter 	adr_MinInterval 	= 8'b00000111;
parameter 	MinIntervalReg 		= adr_MinInterval;
parameter 	adr_AddressSelect 	= 8'b00001000;
parameter 	AddressSelectReg	= adr_AddressSelect;
parameter 	adr_DeviceManufacture 	= 8'b00001001;
parameter 	DeviceManufactureReg 	= adr_DeviceManufacture;
parameter 	adr_Row 		= 8'b10000000;
parameter 	RowReg 			= adr_Row;

initial
   begin

   // define channel_logfile first so have someplace for output go
   if (logfile !== "")		// check if channel_log file defined
      begin
      // logfile define exists so direct output to this logfile

      // don't make logfile same name as default logfile, since $fopen will
      // close logfile if already open and logfile will not contain
      // any output from test, only from channel_monitor module.

      // open logfile
      log = $fopen(logfile);
      if (log == 0)
         begin
           $fdisplay(log,"%6.0f:%0s C%0d ERROR: Could not open %0s log file",
                     $time,align,C_NO,logfile);
	   $stop;
         end

      // add stdout to channel descriptor. This merges the output of logfile
      // with the standard verilog output file. Uncomment this line out if you want
      // the channel monitoring output to go to both channel_logfile AND to
      // stdout and default logfile.
      log = 1 | log;

      end
   else
      begin
      // logfile not defined so direct output to stdout and default logfile

      log = 1;	// set channel descriptor to default

      end

   // The align variable can be used to shift all the output from this
   // module over by the length of the align variable. This allows
   // the output from multiple monitoring modules to be aligned into
   // columns which are associated with a particular module.
   // Do this before outputting to log file.
   repeat (offset) 
     begin
       align = {align," "};
     end

   BusCycleCnt = 1;		// which buscycle of RAVS precondition	
   ReqPacketCnt = 0;		// which cycle of request (0 to 5)
   FoundRequest = 0;		// 1 indicates found a request	
   PacketCnt = 1;		// which request packet
   EnableRequestCnt = 1;	// BusCycleCnt in which can enable looking for start bit
   WritePacketCnt = 10000;
   ReadPacketCnt = 10000;
   WritePacketByte = 0;
   displayon = 1;		// enable writing to log file
   // pad variable is used to align comments
   pad = " -                      ";
   octbyte = 0;
   `ifdef QUICKSTART
     // Initialize delays to quickstart values
     AckWinDelay = 12; 	//  6 clock cycles
     ReadDelay   = 20;	//  10 clock cycles
     AckDelay    =  8;	//  4 clock cycles
     WriteDelay  =  2; 	//  1 clock cycles
   `else
     // Initialize delays to default values upon reset
     AckWinDelay = 24; 	// 12 clock cycles
     ReadDelay   = 18;	//  9 clock cycles
     AckDelay    =  8;	//  4 clock cycles
     WriteDelay  =  8; 	//  4 clock cycles
   `endif
   // Initialize AddressSelect
   AddressSelect[8:0] = 9'b0;
   // Initialize DeviceID
   DeviceId[14:0] = 0;
   // Initialize Wreg* flags
   WregDeviceId = 0;
   WregDelay = 0;
   WregMode = 0;
   WregRefInterval = 0;
   WregRefRow = 0;
   WregAddressSelect = 0;

   $fdisplay(log,"%6.0f:%0s C%0d Monitoring channel %0d",$time,align,C_NO,C_NO);

   if (logfile !== "")		// check if pci_log file defined
     $fdisplay(log,"%6.0f:%0s C%0d Write output to %0s",$time,align,C_NO,logfile);
   else
     $fdisplay(log,"%6.0f:%0s C%0d Write output to default log file",$time,align,C_NO);

   comment("Wait for BusEnable to start monitoring channel activity");
   wait(!BusEnable);
   comment("BusEnable asserted");
   
   // synchronize with falling BusClk so start on even buscycle
   comment("Wait for even buscycle");
   comment("so synchronized");
   @(negedge BusClk)
   comment("Even buscycle detected");
   
   comment("************************");
   comment("Begin monitoring Channel");
   comment("************************");
   comment("(B B BBBBBBBBB)  - Comments");
   comment("(E C DDDDDDDDD)  -");
   comment("(    876543210)  -");
   forever @(posedge BusClk or negedge BusClk)
      begin
      	 text = "- ";
     	 octbyte = 0;

       	 // Ack packet
      	 if (BusCycleCnt == AckPacketCnt)
      	   begin
      	     text = "- Ack[0] ";
             AckPacket0 = ~BusCtrl;
      	   end
      	 if (BusCycleCnt == AckPacketCnt+1)
      	   begin
             AckPacket1 = ~BusCtrl;
	     case ({AckPacket1,AckPacket0})
	       2'b00: 	text = "- Ack[1:0] = Nonexistent ";
	       2'b01:	text = "- Ack[1:0] = Okay ";
	       2'b10:	text = "- Ack[1:0] = Nack ";
	       default:	text = "- Ack[1:0] = Undef ";
	     endcase      	
      	   end

       	 // first serial address packet
      	 if ((BusCycleCnt == SerialAddressCnt)&&(optype == "read"))
      	   begin
      	     text = "- Serial read address 2 ";
      	   end
      	 if ((BusCycleCnt == SerialAddressCnt)&&(optype == "write"))
      	   begin
      	     text = "- Serial write address 2 ";
      	   end

      	 // note beginning of each octbyte in write data packet
      	 // if beginning of packet and after writedelay and opcode is write
	 // and less than 32 octbytes
      	 if ((((WritePacketCnt - BusCycleCnt) % 8) == 0) &&
	     (BusCycleCnt >= WritePacketCnt) && (optype == "write") &&
      	     (((BusCycleCnt - WritePacketCnt)/8)+1 <= 32))
      	   begin
      	     text = {text,"WritePacket "};
      	     // octbyte is 0 except at the beginning of each write packet, when it
	     // is the number of the write packet
      	     octbyte = ((BusCycleCnt - WritePacketCnt)/8)+1;
	   end

      	 // note beginning of each octbyte in read data packet
      	 // if beginning of packet and after readdelay and opcode is read
	 // and less than 32 octbytes
      	 if ((((ReadPacketCnt - BusCycleCnt) % 8) == 0) &&
	     (BusCycleCnt >= ReadPacketCnt) && (optype == "read") &&
      	     (((BusCycleCnt - ReadPacketCnt)/8)+1 <= 32))
      	   begin
      	     text = {text,"ReadPacket "};
      	     // octbyte is 0 except at the beginning of each read packet, when it
	     // is the number of the read packet
      	     octbyte  = ((BusCycleCnt - ReadPacketCnt)/8)+1;
      	   end

      	 // Save first packet of write data for Wreg operations,
      	 // then display new values of Delay, AddressSelect, etc.
         if ((WregDeviceId)||(WregDelay == 1)||(WregMode == 1)||(WregRefInterval == 1)||
             (WregRefRow == 1)||(WregAddressSelect == 1))
            begin
	    if (WritePacketByte == 7)
	       begin
      	      	  // Reset WritePacketByte so stop gathering write data
		  WritePacketByte = 0;
      	      	  if (WregDeviceId == 1)
		     begin
		        DeviceId[14:0] = {WritePacket3[7],WritePacket2[7:0],
                                          WritePacket1[7],WritePacket0[7:1]};
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Wreg DeviceId register:",$time,align,C_NO);
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d DeviceId = %b",$time,align,C_NO,
                                 {WritePacket3[7],WritePacket2[7:0],
                                  WritePacket1[7],WritePacket0[7:1]});
      	                // clear WregDeviceId flag
	                WregDeviceId = 0;
		     end
                  if (WregDelay == 1)
		     begin
      	      	      	`ifdef RDRAM4M
      	      	      	// 4M RDRAM delay register settings
		        case (WritePacket0[5:3])		// AckWinDelay in buscycles
	      	      	   'b101:	AckWinDelay = 'bx;
	      	      	   'b110:	AckWinDelay = 6 * 2;
	      	      	   'b111:	AckWinDelay = 7 * 2;
	      	      	   'b000:	AckWinDelay = 8 * 2;
	      	      	   'b001:	AckWinDelay = 9 * 2;
	      	      	   'b001:	AckWinDelay = 10 * 2;
	      	      	   'b010:	AckWinDelay = 11 * 2;
	      	      	   'b100:	AckWinDelay = 12 * 2;	// default
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal AckWinDelay value of %b",
			                     $time,align,C_NO,WritePacket0[5:3]);
      	      	        endcase
			case (WritePacket1[4:3])		// ReadDelay in buscycles
	      	      	   'b01:	ReadDelay = 9 * 2;	// default
	      	      	   'b10:	ReadDelay = 10 * 2;
	      	      	   'b11:	ReadDelay = 11 * 2;
	      	      	   'b00:	ReadDelay = 12 * 2;
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal ReadDelay value of %b",
			                     $time,align,C_NO,WritePacket1[4:3]);
      	      	        endcase
			case (WritePacket2[4:3])		// AckDelay in buscycles
	      	      	   'b00:	AckDelay = 4 * 2;	// default
	      	      	   'b01:	AckDelay = 5 * 2;
	      	      	   'b10:	AckDelay = 6 * 2;
	      	      	   'b11:	AckDelay = 7 * 2;
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal AckDelay value of %b",
			                     $time,align,C_NO,WritePacket2[4:3]);
      	      	        endcase
			case (WritePacket3[4:3])		// WriteDelay in buscycles
	      	      	   'b01:	WriteDelay = 1 * 2;
	      	      	   'b10:	WriteDelay = 2 * 2;
	      	      	   'b11:	WriteDelay = 3 * 2;
	      	      	   'b00:	WriteDelay = 4 * 2;	// default
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal WriteDelay value of %b",
			                     $time,align,C_NO,WritePacket3[4:3]);
      	      	        endcase
      	      	      	`else
      	      	      	// 16M RDRAM delay register settings
		        case (WritePacket0[5:3])		// AckWinDelay in buscycles
	      	      	   'b101:	AckWinDelay = 5 * 2;
	      	      	   'b110:	AckWinDelay = 6 * 2;
	      	      	   'b111:	AckWinDelay = 7 * 2;
	      	      	   'b000:	AckWinDelay = 8 * 2;
	      	      	   'b001:	AckWinDelay = 9 * 2;
	      	      	   'b001:	AckWinDelay = 10 * 2;
	      	      	   'b010:	AckWinDelay = 11 * 2;
	      	      	   'b100:	AckWinDelay = 12 * 2;	// default
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal AckWinDelay value of %b",
			                     $time,align,C_NO,WritePacket0[5:3]);
      	      	        endcase
			case (WritePacket1[5:3])		// ReadDelay in buscycles
	      	      	   'b111:	ReadDelay = 7 * 2;
	      	      	   'b000:	ReadDelay = 8 * 2;
	      	      	   'b001:	ReadDelay = 9 * 2;	// default
	      	      	   'b010:	ReadDelay = 10 * 2;
	      	      	   'b011:	ReadDelay = 11 * 2;
	      	      	   'b100:	ReadDelay = 12 * 2;
	      	      	   'b101:	ReadDelay = 13 * 2;	// default
	      	      	   'b110:	ReadDelay = 14 * 2;
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal ReadDelay value of %b",
			                     $time,align,C_NO,WritePacket1[4:3]);
      	      	        endcase
			case (WritePacket2[4:3])		// AckDelay in buscycles
	      	      	   'b11:	AckDelay = 3 * 2;
	      	      	   'b00:	AckDelay = 4 * 2;	// default
	      	      	   'b01:	AckDelay = 5 * 2;
	      	      	   'b10:	AckDelay = 6 * 2;
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal AckDelay value of %b",
			                     $time,align,C_NO,WritePacket2[4:3]);
      	      	        endcase
			case (WritePacket3[5:3])		// WriteDelay in buscycles
	      	      	   'b001:	WriteDelay = 1 * 2;
	      	      	   'b010:	WriteDelay = 2 * 2;
	      	      	   'b011:	WriteDelay = 3 * 2;
	      	      	   'b100:	WriteDelay = 4 * 2;	// default
	      	      	   'b101:	WriteDelay = 5 * 2;
	      	      	   'b110:	WriteDelay = 6 * 2;
	      	      	   'b111:	WriteDelay = 7 * 2;
	      	      	   'b000:	WriteDelay = 8 * 2;	// default
	      	      	   default: $fdisplay(log,"%6.0f:%0s C%0d Illegal WriteDelay value of %b",
			                     $time,align,C_NO,WritePacket3[4:3]);
      	      	        endcase
			`endif
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Wreg Delay register:",$time,align,C_NO);
      	                $fdisplay(log,"%6.0f:%0s C%0d AckWinDelay=%0d,ReadDelay=%0d",
      	      	      	      	  $time,align,C_NO,AckWinDelay,ReadDelay);
      	                $fdisplay(log,"%6.0f:%0s C%0d AckDelay=%0d,WriteDelay=%0d",
      	      	      	      	  $time,align,C_NO,AckDelay,WriteDelay);
      	      	      	// clear WregDelay flag
	                WregDelay = 0;
		     end
      	      	  if (WregMode == 1)
		     begin
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Wreg Mode register:",$time,align,C_NO);
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d CE=%b,X2=%b,SK=%b,AS=%b,DE=%b,RE=%b,C[5:0]=%b",
      	      	      	      	 $time,align,C_NO,WritePacket0[7],WritePacket0[6],WritePacket0[3],
				 WritePacket0[2],WritePacket0[1],WritePacket0[0],
      	      	      	      	 {WritePacket1[7],WritePacket2[7],WritePacket3[7],
      	      	      	      	  WritePacket1[6],WritePacket2[6],WritePacket3[6]});
      	                // clear WregMode flag
	                WregMode = 0;
		     end
      	      	  if (WregRefInterval == 1)
		     begin
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Wreg RefInterval register:",$time,align,C_NO);
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d RefLoad = %b",$time,align,C_NO,
                                 {WritePacket3[7],WritePacket2[7:0]});
      	                // clear WregRefInterval flag
	                WregRefInterval = 0;
		     end
      	      	  if (WregRefRow == 1)
		     begin
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Wreg RefRow register:",$time,align,C_NO);
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Bank = %b, Row = %b",$time,align,C_NO,
                                 WritePacket1[2],WritePacket0[7:0]);
      	                // clear WregRefRow flag
	                WregRefRow = 0;
		     end
                  if (WregAddressSelect == 1)
		     begin
      	      	      	AddressSelect[8:1] = WritePacket0[7:0];
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d Wreg AddressSelect register:",$time,align,C_NO);
      	      	      	$fdisplay(log,"%6.0f:%0s C%0d AddressSelect[8:1] = %b",
      	      	      	      	  $time,align,C_NO,AddressSelect[8:1]);
      	                // clear WregAddressSelect flag
	                WregAddressSelect = 0;
		     end
                  WritePacket0 = 0;
                  WritePacket1 = 0;
                  WritePacket2 = 0;
                  WritePacket3 = 0;
                  WritePacket4 = 0;
                  WritePacket5 = 0;
                  WritePacket6 = 0;
                  WritePacket7 = 0;
	       end	// if (WritePacketByte == 7)
	    if (WritePacketByte == 6)
	       begin
	          WritePacket6 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    if (WritePacketByte == 5)
	       begin
	          WritePacket5 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    if (WritePacketByte == 4)
	       begin
	          WritePacket4 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    if (WritePacketByte == 3)
	       begin
	          WritePacket3 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    if (WritePacketByte == 2)
	       begin
	          WritePacket2 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    if (WritePacketByte == 1)
	       begin
	          WritePacket1 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    if ((WritePacketByte == 0)&&(octbyte == 1))
	       begin
	          WritePacket0 = ~{BusData};
		  WritePacketByte = WritePacketByte + 1;
	       end
	    end	// if ((WregDelay == 1)||(WregAddressSelect == 1))

      	 BusCycleCnt = BusCycleCnt + 1;

       	 if ((BusCycleCnt >= EnableRequestCnt) && (FoundRequest == 1))
	    begin
      	       text = {text,"End of Ack Window "};
	    end
      	 if ((~BusCtrl === 1'b1) && (FoundRequest == 0) && (BusCycleCnt % 2 == 1))
      	    begin
      	       // found start bit in even buscycle
      	       text = {text,"Start bit "};
               displayon = 1;	// enable/re-enable writing to log file when find start bit
               idlecount = 0;	// reset count of idle buscycles
	    end

         // if SUPPRESS_CHANNEL defined, suppresses displaying the value of the channel,
	 // which ends up being a large portion of the log file output.
         if (!$test$plusargs("SUPPRESS_CHANNEL"))
           begin
             if (displayon == 1)
               begin
                 // Output channel data
                   if (octbyte == 0)
            	   // normal case
            	   $fdisplay(log,"%6.0f:%0s C%0d (%b %b %b)  %0s",
            	       	   $time,align,C_NO,~BusEnable,~BusCtrl,~BusData,text);
                   else
            	   // only if read or write and beginning of a data packet
            	   $fdisplay(log,"%6.0f:%0s C%0d (%b %b %b)  %0s %0d",
            	          $time,align,C_NO,~BusEnable,~BusCtrl,~BusData,text,octbyte);
               end
      	   end
	 
         // count buscycles with null text as idle
         if (text == "- ")
	   begin
	     idlecount = idlecount + 1;	// consecutive idle buscycles
	   end
	 else
	   begin
	     idlecount = 0;
	   end

         if (idlecount == 10)
	   begin
             if (!$test$plusargs("SUPPRESS_CHANNEL"))
               begin
                 $fdisplay(log,"%6.0f:%0s C%0d Disable Channel monitor until next transaction",
          	       $time,align,C_NO);
	       end
      	     displayon = 0;
	   end

      	 if (ReqPacketCnt == 5)
      	    begin
      	       ReqPacket5 = ~{BusCtrl,BusData};
      	       ReqPacketCnt = ReqPacketCnt + 1;
      	       // disassemble request
      	       opcode[5:0] = {ReqPacket1[8],ReqPacket3[9],ReqPacket1[9],
      	      	      	      ReqPacket0[8],ReqPacket2[9],ReqPacket4[9]};
      	       Adr[35:0] = {ReqPacket3[8:0],ReqPacket2[8:0],ReqPacket1[7:0],
      	      	      	    ReqPacket0[7:0],ReqPacket5[1:0]};
               if (!$test$plusargs("SUPPRESS_CHANNEL"))
                 begin
                   comment("************************");
      	           $fdisplay(log,"%6.0f:%0s C%0d Section %0d - Decode Request packet %0d",
      	       	             $time,align,C_NO,Section,PacketCnt);
      	           $fdisplay(log,"%6.0f:%0s C%0d %0s op",$time,align,C_NO,DecodeOp(opcode));
      	           $fdisplay(log,"%6.0f:%0s C%0d op[3:0]=%b,opX[1:0]=%b",
      	       	             $time,align,C_NO,opcode[5:2],opcode[1:0]);
//     	           $fdisplay(log,"%6.0f:%0s C%0d RegUnimp[7:0]=%b",$time,align,C_NO,
//     	       	             {ReqPacket5[8],ReqPacket5[7],ReqPacket4[8],ReqPacket4[7],
//     	      	             ReqPacket4[3],ReqPacket4[2],ReqPacket4[1],ReqPacket4[0]});
      	           $fdisplay(log,"%6.0f:%0s C%0d Count[7:3,2:0]=%b %b",
      	       	             $time,align,C_NO,{ReqPacket5[6],ReqPacket4[6],ReqPacket5[5],ReqPacket4[5],ReqPacket5[4]},
      	      	             {ReqPacket4[4],ReqPacket5[3],ReqPacket5[2]});
      	           $fdisplay(log,"%6.0f:%0s C%0d Addr[2:0]=%b",$time,align,C_NO,{ReqPacket0[0],ReqPacket5[1:0]});
                 end
      	       PacketCnt = PacketCnt + 1;

      	       if ((opcode === RregOp)||(opcode === WregOp)||
      	       	   (opcode === WregBOp)||(opcode === WregBnOp))
      	       	  begin
      	       	  // register operation
                  if (!$test$plusargs("SUPPRESS_CHANNEL"))
                    begin
         	      $fdisplay(log,"%6.0f:%0s C%0d Addr[9:2]=%b(%0s reg)",
      	       	     	        $time,align,C_NO,ReqPacket0[7:0],DecodeAddr(ReqPacket0[7:0]));
                    end

      	      	  // if Wreg Delay or AddressSelect register, set flag
      	          if ((opcode === WregOp)||(opcode === WregBOp)||(opcode === WregBnOp))
		     case (DecodeAddr(ReqPacket0[7:0]))
		        "DeviceId":		WregDeviceId = 1;
		        "Delay":		WregDelay = 1;
		        "Mode":			WregMode = 1;
		        "RefInterval":		WregRefInterval = 1;
		        "RefRow":		WregRefRow = 1;
		        "AddressSelect":	WregAddressSelect = 1;
		     endcase		  

      	          // unpack virtual address in request into physical address and display
      	          unpack(Adr[35:3]);
		  end
      	       else
	          begin
      	       	  // memory operation
      	          // unpack virtual address in request into physical address and display
      	          unpack(Adr[35:3]);
		  end

      	       // read or write operation
      	       if ((opcode === RseqOp)||(opcode === RseqxOp)||(opcode === RseqAltOp)||
      	           (opcode === RnsqOp)||(opcode === RnsqxOp)||(opcode === RnsqAltOp)||
      	           (opcode === Rx1Op) ||(opcode === Rx2Op)  ||(opcode === Rx3Op)||
      	           (opcode === RregOp))
      	       	  begin
      	      	    optype = "read";
		  end
      	       else if ((opcode === WseqNpbOp)||(opcode === WseqNpbxOp)||(opcode === WseqNpbAltOp)||
      	           (opcode === WseqDpbOp)||(opcode === WseqDpbxOp)||(opcode === WseqDpbAltOp)||
      	       	   (opcode === WseqBpbOp)||(opcode === WseqBpbxOp)||(opcode === WseqBpbAltOp)||
      	       	   (opcode === WseqMpbOp)||(opcode === WseqMpbxOp)||(opcode === WseqMpbAltOp)||
      	       	   (opcode === WseqNpbDpbx1Op) ||(opcode === WseqNpbDpbx2Op)  ||(opcode === WseqNpbDpbx3Op)||
      	       	   (opcode === WseqNpbBpbx1Op) ||(opcode === WseqNpbBpbx2Op)  ||(opcode === WseqNpbBpbx3Op)||
      	       	   (opcode === WseqBpbMpbx1Op) ||(opcode === WseqBpbMpbx2Op)  ||(opcode === WseqBpbMpbx3Op)||
      	       	   (opcode === WseqDpbMpbx1Op) ||(opcode === WseqDpbMpbx2Op)  ||(opcode === WseqDpbMpbx3Op)||
      	       	   (opcode === Wseqx1Op) ||(opcode === Wseqx2Op)  ||(opcode === Wseqx3Op)||
      	           (opcode === WregOp)||
      	       	   (opcode === WnsqNpbOp)||(opcode === WnsqNpbxOp)||(opcode === WnsqNpbAltOp)||
      	       	   (opcode === WnsqDpbOp)||(opcode === WnsqDpbxOp)||(opcode === WnsqDpbAltOp)||
      	       	   (opcode === WnsqBpbOp)||(opcode === WnsqBpbxOp)||(opcode === WnsqBpbAltOp)||
      	       	   (opcode === WnsqMpbOp)||(opcode === WnsqMpbxOp)||(opcode === WnsqMpbAltOp)||
      	       	   (opcode === WnsqNpbDpbx1Op) ||(opcode === WnsqNpbDpbx2Op)  ||(opcode === WnsqNpbDpbx3Op)||
      	       	   (opcode === WnsqNpbBpbx1Op) ||(opcode === WnsqNpbBpbx2Op)  ||(opcode === WnsqNpbBpbx3Op)||
      	       	   (opcode === WnsqBpbMpbx1Op) ||(opcode === WnsqBpbMpbx2Op)  ||(opcode === WnsqBpbMpbx3Op)||
      	       	   (opcode === WnsqDpbMpbx1Op) ||(opcode === WnsqDpbMpbx2Op)  ||(opcode === WnsqDpbMpbx3Op)||
      	       	   (opcode === Wnsqx1Op) ||(opcode === Wnsqx2Op)  ||(opcode === Wnsqx3Op)||
      	       	   (opcode === WbnsNpbOp)||(opcode === WbnsNpbxOp)||(opcode === WbnsNpbAltOp)||
      	       	   (opcode === WbnsDpbOp)||(opcode === WbnsDpbxOp)||(opcode === WbnsDpbAltOp)||
      	       	   (opcode === WbnsMpbOp)||(opcode === WbnsMpbxOp)||(opcode === WbnsMpbAltOp)||
      	       	   (opcode === Wbnsx1Op) ||(opcode === Wbnsx2Op)  ||(opcode === Wbnsx3Op)||
      	       	   (opcode === Wbnsx4Op) ||(opcode === Wbnsx5Op)  ||(opcode === Wbnsx6Op)||
      	           (opcode === WregBOp))
      	       	  begin
      	      	    optype = "write";
		  end
      	       else if (opcode === WregBnOp)
      	       	  begin
      	      	    optype = "WregBn";
		  end
      	       else
      	       	  begin
      	      	    optype = "Rsrv";
		  end

               if (!$test$plusargs("SUPPRESS_CHANNEL"))
                 begin
      	           // delay register values
      	           $fdisplay(log,"%6.0f:%0s C%0d AckWinDelay=%0d,ReadDelay=%0d",
                         $time,align,C_NO,AckWinDelay,ReadDelay);
      	           $fdisplay(log,"%6.0f:%0s C%0d AckDelay=%0d,WriteDelay=%0d",
                         $time,align,C_NO,AckDelay,WriteDelay);
                 end

      	      // Reset ReqPacketCnt for next request
      	      ReqPacketCnt = 0;
      	      // Time is end of current request. Device is inhibited from looking
	      // for new start bit until after AckWinDelay following current request
      	      // So wait AckWinDelay buscycles before looking for next start bit
       	      // Use non-blocking assignment to schedule this event in future.
      	      // non-blocking assignment crashes dumpvars
	      // FoundRequest<=repeat(AckWinDelay-1)@(posedge BusClk or negedge BusClk)0;
	      EnableRequestCnt = BusCycleCnt + AckWinDelay;
//      	      $fdisplay(log,"%6.0f:%0s C%0d Ack window ends = %0d (end of request) + %0d (AckWinDelay) = %0d",
//      	      	      $time,align,C_NO,BusCycleCnt,AckWinDelay,EnableRequestCnt);

      	      // beginning of ack packet
      	      AckPacketCnt = BusCycleCnt + AckDelay;
//      	      $fdisplay(log,"%6.0f:%0s C%0d Ack packet = %0d (end of request) + %0d (AckDelay) = %0d",
//      	      	      $time,align,C_NO,BusCycleCnt,AckDelay,BusCycleCnt+AckDelay);

      	      if (optype == "write")
	        begin
      	        // beginning of write data packet
      	        WritePacketCnt = BusCycleCnt + WriteDelay;
      	      	// serial write offset is 10 bc (5 CC) plus 8 since first octbyte has no serial adr
      	        SerialAddressCnt = WritePacketCnt - 10 + 8;
//      	        $fdisplay(log,"%6.0f:%0s C%0d write data = %0d (end of request) + %0d (WriteDelay) = %0d",
//      	      	      $time,align,C_NO,BusCycleCnt,WriteDelay,WritePacketCnt);
		end

      	      if (optype == "read")
	        begin
      	        // beginning of read data packet
      	        ReadPacketCnt = BusCycleCnt + ReadDelay;
      	      	// serial write offset is 26 bc (13 CC) plus 8 since first octbyte has no serial adr
      	        SerialAddressCnt = ReadPacketCnt - 26 + 8;
//      	        $fdisplay(log,"%6.0f:%0s C%0d read data = %0d (end of request) + %0d (ReadDelay) = %0d",
//      	      	      $time,align,C_NO,BusCycleCnt,ReadDelay,ReadPacketCnt);

		end
               if (!$test$plusargs("SUPPRESS_CHANNEL"))
                 begin
                   comment("************************");
		 end
	    end
      	 if (ReqPacketCnt == 4)
      	    begin
      	       ReqPacket4 = ~{BusCtrl,BusData};
      	       ReqPacketCnt = ReqPacketCnt + 1;
	    end
      	 if (ReqPacketCnt == 3)
      	    begin
      	       ReqPacket3 = ~{BusCtrl,BusData};
      	       ReqPacketCnt = ReqPacketCnt + 1;
	    end
      	 if (ReqPacketCnt == 2)
      	    begin
      	       ReqPacket2 = ~{BusCtrl,BusData};
      	       ReqPacketCnt = ReqPacketCnt + 1;
	    end
      	 if (ReqPacketCnt == 1)
      	    begin
      	       ReqPacket1 = ~{BusCtrl,BusData};
      	       ReqPacketCnt = ReqPacketCnt + 1;
	    end

       	 if ((BusCycleCnt >= EnableRequestCnt) && (FoundRequest == 1))
	    begin
	       FoundRequest = 0;
	    end

      	 if ((~BusCtrl === 1'b1) && (FoundRequest == 0) && (BusCycleCnt % 2 == 1))
      	    begin
      	       // found start bit in even buscycle
      	       ReqPacket0 = ~{BusCtrl,BusData};
      	       ReqPacketCnt = ReqPacketCnt + 1;
      	       // disable search for start bit until after this request's ack window
      	       FoundRequest = 1;
	       EnableRequestCnt = BusCycleCnt + 6 + AckWinDelay;
	    end
      end
end

// ****************************************************************************
// monitor other signals on channel
// ****************************************************************************

// display changes in SIn
initial
begin
   forever @(posedge SIn or negedge SIn)
      begin
      	 $fdisplay(log,"%6.0f:%0s C%0d                  - SIn=%b",
           $time,align,C_NO,SIn);
      end
end

// display changes in SOut
initial
begin
   forever @(posedge SOut or negedge SOut)
      begin
      	 $fdisplay(log,"%6.0f:%0s C%0d                  - SOut=%b",
           $time,align,C_NO,SOut);
      end
end

// ****************************************************************************
// subroutines/functions
// ****************************************************************************

task comment;    	// display comments in standardized manner
   input       	     	textstring;
   reg [8*100:1]	textstring;
   begin
      $fdisplay(log,"%6.0f:%0s C%0d %0s",$time,align,C_NO,textstring);
   end
endtask

// Display mnemonic corresponding to register address
function [25*8:0] DecodeAddr;
   input register;
   reg [9:2] register;
   begin
      case (register)
      	 DeviceTypeReg:    	DecodeAddr = "DeviceType";
      	 DeviceIdReg:     	DecodeAddr = "DeviceId";
      	 DelayReg:    		DecodeAddr = "Delay";
      	 ModeReg:    		DecodeAddr = "Mode";
      	 RefIntervalReg:     	DecodeAddr = "RefInterval";
      	 RefRowReg:     	DecodeAddr = "RefRow";
      	 RasIntervalReg:     	DecodeAddr = "RasInterval";
      	 MinIntervalReg:     	DecodeAddr = "MinInterval";
      	 AddressSelectReg:     	DecodeAddr = "AddressSelect";
      	 DeviceManufactureReg:  DecodeAddr = "DeviceManufacture";
      	 RowReg:    		DecodeAddr = "Row";
      	 default:		DecodeAddr = "unknown";
      endcase
   end
endfunction

// Display mnemonic corresponding to Op[3:0] and OpX[1:0]
function [60*8:0] DecodeOp;
   input opcode;
   reg [5:0] opcode;
   begin
      case (opcode)
      	 6'b000000,
      	 6'b000100,
      	 6'b000x00:	DecodeOp = "Rseq[Alt]";
      	 6'b000001,
      	 6'b000101,
      	 6'b000x01:	DecodeOp = "Rnsq[Alt]";

      	 6'b00000x,
	 6'b00010x,
	 6'b000x0x:	DecodeOp = "R{seq,nsq}";

      	 6'b000010,
      	 6'b000011,
      	 6'b00001x:	DecodeOp = "Rsrv";

      	 6'b000110,
      	 6'b000111,
      	 6'b00011x:	DecodeOp = "Rsrv";

      	 6'b001000,
      	 6'b001001,
      	 6'b001010,
      	 6'b001011,
      	 6'b0010xx:	DecodeOp = "Rsrv";

      	 6'b001100,
      	 6'b001101,
      	 6'b001110,
      	 6'b001111,
      	 6'b0011xx:	DecodeOp = "Rsrv";

      	 6'b010000,
      	 6'b010100,
      	 6'b010x00:	DecodeOp = "WseqNpb[Alt] ";
      	 6'b010001,
      	 6'b010101,
      	 6'b010x01:	DecodeOp = "WseqDpb[Alt] ";
      	 6'b010010,
      	 6'b010110,
      	 6'b010x10:	DecodeOp = "WseqBpb[Alt] ";
      	 6'b010011,
      	 6'b010111,
      	 6'b010x11:	DecodeOp = "WseqMpb[Alt] ";
	 
      	 6'b01000x,
      	 6'b01010x,
      	 6'b010x0x:	DecodeOp = "Wseq{Npb,Dpb}";
	 6'b0100x0,
	 6'b0101x0,
	 6'b010xx0:	DecodeOp = "Wseq{Npb,Bpb}";      
	 6'b01001x,
	 6'b01011x,
	 6'b010x1x:	DecodeOp = "Wseq{Bpb,Mpb}";
	 6'b0100x1,
	 6'b0101x1,
	 6'b010xx1:	DecodeOp = "Wseq{Dpb,Mpb}";      
	 6'b0100xx,
	 6'b0101xx,
	 6'b010xxx:	DecodeOp = "Wseq{Npb,Dpb,Bpb,Mpb}";

      	 6'b011000:	DecodeOp = "Rreg";
      	 6'b011001:	DecodeOp = "Rsrv";
      	 6'b011010,
      	 6'b011011,
      	 6'b01101x:	DecodeOp = "Rsrv";

      	 6'b011100:	DecodeOp = "Wreg";
      	 6'b011101:	DecodeOp = "Rsrv";
      	 6'b011110,
      	 6'b011111,
      	 6'b01111x:	DecodeOp = "Rsrv";

      	 6'b100000,
      	 6'b100100,
      	 6'b100x00:	DecodeOp = "WnsqNpb[Alt] ";
      	 6'b100001,
      	 6'b100101,
      	 6'b100x01:	DecodeOp = "WnsqDpb[Alt] ";
      	 6'b100010,
      	 6'b100110,
      	 6'b100x10:	DecodeOp = "WnsqBpb[Alt] ";
      	 6'b100011,
      	 6'b100111,
      	 6'b100x11:	DecodeOp = "WnsqMpb[Alt] ";
	 
      	 6'b10000x,
      	 6'b10010x,
      	 6'b100x0x:	DecodeOp = "Wnsq{Npb,Dpb}";
	 6'b1000x0,
	 6'b1001x0,
	 6'b100xx0:	DecodeOp = "Wnsq{Npb,Bpb}";      
	 6'b10001x,
	 6'b10011x,
	 6'b100x1x:	DecodeOp = "Wnsq{Bpb,Mpb}";
	 6'b1000x1,
	 6'b1001x1,
	 6'b100xx1:	DecodeOp = "Wnsq{Dpb,Mpb}";      
	 6'b1000xx,
	 6'b1001xx,
	 6'b100xxx:	DecodeOp = "Wnsq{Npb,Dpb,Bpb,Mpb}";

      	 6'b101000,
      	 6'b101001,
      	 6'b101010,
      	 6'b101011,
      	 6'b1010xx:	DecodeOp = "Rsrv";

      	 6'b101100,
      	 6'b101101,
      	 6'b101110,
      	 6'b101111,
      	 6'b1011xx:	DecodeOp = "Rsrv";

      	 6'b110000,
      	 6'b110100,
      	 6'b110x00:	DecodeOp = "WbnsNpb[Alt] ";
      	 6'b110001,
      	 6'b110101,
      	 6'b110x01:	DecodeOp = "WbnsDpb[Alt] ";
      	 6'b110010:	DecodeOp = "Rsrv";
      	 6'b110011,
      	 6'b110111,
      	 6'b110x11:	DecodeOp = "WbnsMpb[Alt] ";
	 
      	 6'b11000x,
	 6'b11010x,
	 6'b110x0x:	DecodeOp = "Wbns{Npb,Dpb}";
	 6'b1100x1,
	 6'b1101x1,
	 6'b110xx1:	DecodeOp = "Wbns{Dpb,Mpb}";

      	 6'b110110:	DecodeOp = "Rsrv";
	 
      	 6'b111000:	DecodeOp = "WregBn (nop)";
      	 6'b111001:	DecodeOp = "Rsrv";
      	 6'b111010,
      	 6'b111011,
      	 6'b11101x:	DecodeOp = "Rsrv";

      	 6'b111100:	DecodeOp = "WregB";
      	 6'b111101:	DecodeOp = "Rsrv";
      	 6'b111110,
      	 6'b111111,
      	 6'b11111x:	DecodeOp = "Rsrv";

      	 default:	DecodeOp = "unknown";
      endcase
   end
endfunction

// unpack
// given virtual Adr[35:3] in the request packet, unpack and generate
// physical AdrS[35:3] {deviceid[14:0],row[8:0],col[7:0]} based on
// AddressSelect register.
task unpack;
  input Adr;
  reg [35:3]	Adr;		// virtual Adr
  reg [14:0]	deviceid;
  reg		bank;
  reg [8:0]	row;
  reg [7:0]	col;
  begin
    deviceid[14:8] = Adr[35:29];

    deviceid[7] = AddressSelect[8] ? Adr[19] : Adr[28];
    deviceid[6] = AddressSelect[7] ? Adr[18] : Adr[27];
    deviceid[5] = AddressSelect[6] ? Adr[17] : Adr[26];
    deviceid[4] = AddressSelect[5] ? Adr[16] : Adr[25];
    deviceid[3] = AddressSelect[4] ? Adr[15] : Adr[24];
    deviceid[2] = AddressSelect[3] ? Adr[14] : Adr[23];
    deviceid[1] = AddressSelect[2] ? Adr[13] : Adr[22];
    deviceid[0] = AddressSelect[1] ? Adr[12] : Adr[21];

    bank        = AddressSelect[0] ? Adr[11] : Adr[20];

    row[8] = AddressSelect[8] ? Adr[28] : Adr[19];
    row[7] = AddressSelect[7] ? Adr[27] : Adr[18];
    row[6] = AddressSelect[6] ? Adr[26] : Adr[17];
    row[5] = AddressSelect[5] ? Adr[25] : Adr[16];
    row[4] = AddressSelect[4] ? Adr[24] : Adr[15];
    row[3] = AddressSelect[3] ? Adr[23] : Adr[14];
    row[2] = AddressSelect[2] ? Adr[22] : Adr[13];
    row[1] = AddressSelect[1] ? Adr[21] : Adr[12];
    row[0] = AddressSelect[0] ? Adr[20] : Adr[11];
    col[7:0] = Adr[10:3];

    if (!$test$plusargs("SUPPRESS_CHANNEL"))
      begin
        $fdisplay(log,"%6.0f:%0s C%0d deviceid[14:0]=%b",$time,align,C_NO,deviceid[14:0]);
        $fdisplay(log,"%6.0f:%0s C%0d bank=%b,row[8:0]=%b(#%h)",
      	     $time,align,C_NO,bank,row[8:0],row[8:0]);
        $fdisplay(log,"%6.0f:%0s C%0d col[7:0]=%b(#%h)",
      	     $time,align,C_NO,col[7:0],col[7:0]);
        $fdisplay(log,"%6.0f:%0s C%0d AdrS[35:3]=%b %b %b %b",
      	     $time,align,C_NO,deviceid[14:8],{deviceid[7:0],bank},row[8:0],col[7:0]);
      end
    AdrS[35:29] = deviceid[14:8];
    AdrS[28:21] = deviceid[7:0];
    AdrS[20]    = bank;
    AdrS[19:11] = row[8:0];
    AdrS[10:3]  = col[7:0];
    if (!$test$plusargs("SUPPRESS_CHANNEL"))
      begin
        $fdisplay(log,"%6.0f:%0s C%0d AddressSelect[8:0]=%b %b",
                  $time,align,C_NO,AddressSelect[8:0],AddressSelect[8:0]);
        $fdisplay(log,"%6.0f:%0s C%0d Adr[35:0] =%b %b %b %b",
      	          $time,align,C_NO,Adr[35:29],Adr[28:20],Adr[19:11],Adr[10:3]);
      end

  end
endtask

endmodule

`endif					 // MON_CHANNEL