mi_tab.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: mi_tab.v
// description: dumps out mi i/o .tab file
//
// designer: Tony DeLaurier
// date: 12/08/94
//
////////////////////////////////////////////////////////////////////////
module mi_tab();
integer tab_file_ptr;
// open tab file and dump header
initial
begin
tab_file_ptr = $fopen("mi000.tab");
// dump out header
$fwriteh(tab_file_ptr, "#\n");
$fwriteh(tab_file_ptr, "# mi tab file\n");
$fwriteh(tab_file_ptr, "#\n");
$fwriteh(tab_file_ptr, "clock @C 1(8) 0(8)\n");
$fwriteh(tab_file_ptr, "reset_l @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_read_enable @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_write_enable @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_grant @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "dbus_read_enable @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "dbus_write_enable @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "dma_start @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "dma_last @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "sys_ad_in_h[31:0] @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "sys_cmd_in_h[4:0] @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "p_valid_l @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_select[1:0] @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_command[2:0] @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "pi_interrupt @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "vi_interrupt @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "ai_interrupt @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "si_interrupt @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "sp_interrupt @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "pipe_busy @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "version[31:0] @I @E 2 @C clock\n");
$fwriteh(tab_file_ptr, "dma_request @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "write_request @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "read_request @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "sys_ad_out_h[31:0] @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "sys_cmd_out_h[4:0] @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "e_valid_l @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "e_ok_l @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "int_l @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "sys_ad_enable_l @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_data[31:0] @B cbus_data_oe 1 @E 5 @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_data_oe @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "cbus_dummy @I @E 0 @C clock\n");
$fwriteh(tab_file_ptr, "dbus_data[63:0] @B dbus_data_oe 1 @E 5 @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "dbus_data_oe @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "dbus_dummy @I @E 0 @C clock\n");
$fwriteh(tab_file_ptr, "ebus_data[7:0] @B ebus_data_oe 1 @E 5 @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "ebus_data_oe @O @S 15 @C clock\n");
$fwriteh(tab_file_ptr, "ebus_dummy @I @E 0 @C clock\n");
$fwriteh(tab_file_ptr, "\n");
end // initial
// dump mi at pos edge of clock
always @(posedge reality.rcp_0.mi_0.clock)
begin
$fwriteh(tab_file_ptr,
reality.rcp_0.mi_0.reset_l,," ",
reality.rcp_0.mi_0.cbus_read_enable,,
reality.rcp_0.mi_0.cbus_write_enable,,
reality.rcp_0.mi_0.cbus_grant,,
reality.rcp_0.mi_0.dbus_read_enable,,
reality.rcp_0.mi_0.dbus_write_enable,,
reality.rcp_0.mi_0.dma_start,,
reality.rcp_0.mi_0.dma_last,,
"0x", reality.rcp_0.mi_0.sys_ad_in_h,,
"0x", reality.rcp_0.mi_0.sys_cmd_in_h,,
reality.rcp_0.mi_0.p_valid_l,,
"0x", reality.rcp_0.mi_0.cbus_select,,
"0x", reality.rcp_0.mi_0.cbus_command,,
reality.rcp_0.mi_0.pi_interrupt,,
reality.rcp_0.mi_0.vi_interrupt,,
reality.rcp_0.mi_0.ai_interrupt,,
reality.rcp_0.mi_0.si_interrupt,,
reality.rcp_0.mi_0.sp_interrupt,,
reality.rcp_0.mi_0.pipe_busy,,
"0x", reality.rcp_0.mi_0.version,," ",
reality.rcp_0.mi_0.dma_request,,
reality.rcp_0.mi_0.write_request,,
reality.rcp_0.mi_0.read_request,,
"0x", reality.rcp_0.mi_0.sys_ad_out_h,,
"0x", reality.rcp_0.mi_0.sys_cmd_out_h,,
reality.rcp_0.mi_0.e_valid_l,,
reality.rcp_0.mi_0.e_ok_l,,
reality.rcp_0.mi_0.int_l,,
reality.rcp_0.mi_0.sys_ad_enable_l,," ",
"0x", reality.rcp_0.mi_0.cbus_data,,
reality.rcp_0.mi_0.cbus_write_enable,,
reality.rcp_0.mi_0.cbus_write_enable,,
"0x", reality.rcp_0.mi_0.dbus_data,,
reality.rcp_0.mi_0.dbus_write_enable,,
reality.rcp_0.mi_0.dbus_write_enable,,
"0x", reality.rcp_0.mi_0.ebus_data,,
reality.rcp_0.mi_0.dbus_write_enable,,
reality.rcp_0.mi_0.dbus_write_enable,,
"\n");
end // always
endmodule // mi_tab