sync.v
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module sync(bus_clk, reset_l, test, ad16_data, ad16_read, ad16_write, mask_ad16rw);
`include "reality.vh"
`include "define.vh"
`define ad16_ByPass ad16_data[0]
`define ad16_SynClkSet ad16_data[1]
`define ad16_BISTMode ad16_data[2]
`define ad16_IOSTMode ad16_data[3]
`define ad16_CCtli0 ad16_data[4]
`define ad16_CCtli1 ad16_data[5]
`define ad16_CCtli2 ad16_data[6]
`define ad16_CCtli3 ad16_data[7]
`define ad16_CCtli4 ad16_data[8]
`define ad16_CCtli5 ad16_data[9]
`define ad16_CCtlEn ad16_data[10]
`define ad16_CCtlLd ad16_data[11]
`define ad16_RACReset ad16_data[12]
`define ad16_ExtBE ad16_data[13]
`define ad16_DelayIn ad16_data[14]
`define ad16_BISTFlag ad16_read
`define ad16_DelayOut ad16_write
input bus_clk;
input ad16_read;
input ad16_write;
output reset_l;
output test;
output mask_ad16rw;
output [AD16_DATA_SIZE-1:0] ad16_data;
reg reset_l;
reg test;
reg system_ready;
reg [AD16_DATA_SIZE-1:0] ad16_data;
reg mask_ad16rw;
reg test_rac_bist;
reg test_delay;
reg test_bypass;
reg [19:0] wait_cnt;
initial wait_cnt = 'h0;
initial begin
mask_ad16rw <= 1'b1;
test_rac_bist = 1'b0;
test_delay = 1'b0;
test_bypass = 1'b0;
if ($test$plusargs("test_rac_bist")) test_rac_bist = 1'b1;
if ($test$plusargs("test_delay")) test_delay = 1'b1;
if ($test$plusargs("test_bypass")) test_bypass = 1'b1;
system_ready <= LOW;
if (test_rac_bist)
begin
Norm_Reset(1'b1);
$display("Running RAC BIST test");
mask_ad16rw <= 1'b1;
NormToMUX;
RAC_BIST_TEST;
repeat (32) @(posedge bus_clk);
$finish;
end
else
if (test_delay)
begin
Norm_Reset(1'b1);
$display("Running DELAY CHAIN test");
mask_ad16rw <= 1'b1;
NormToMUX;
DELAY_TEST;
repeat (32) @(posedge bus_clk);
$finish;
end
else
if (test_bypass)
begin
$display("GOING TO BYPASS MODE");
NormToBYP;
system_ready <= HIGH;
end
else
begin
//Norm_Reset(1'b0);
Norm_Reset_sequence(1'b0);
$display("SYNC TO NORM MODE");
//Norm_BYP_Norm;
system_ready <= HIGH;
end
end
/***************************************************
* Tasks
***************************************************/
task Norm_Reset;
input bypass;
begin
reset_l <= LOW;
test <= LOW;
`ad16_ByPass <= bypass;
`ad16_SynClkSet <= 1'b0;
`ad16_BISTMode <= 1'b0;
`ad16_IOSTMode <= 1'b0;
`ad16_CCtli0 <= 1'b0;
`ad16_CCtli1 <= 1'b0;
`ad16_CCtli2 <= 1'b0;
`ad16_CCtli3 <= 1'b0;
`ad16_CCtli4 <= 1'b0;
`ad16_CCtli5 <= 1'b0;
`ad16_CCtlEn <= 1'b0;
`ad16_CCtlLd <= 1'b1;
`ad16_RACReset <= 1'b1;
`ad16_ExtBE <= 1'b0;
`ad16_DelayIn <= 1'b1; repeat (4) @(posedge bus_clk);
end
endtask
task Norm_Reset_sequence;
input bypass;
begin
reset_l <= LOW;
test <= LOW;
`ad16_ByPass <= bypass;
`ad16_SynClkSet <= 1'b0;
`ad16_BISTMode <= 1'b0;
`ad16_IOSTMode <= 1'b0;
`ad16_CCtli0 <= 1'b0;
`ad16_CCtli1 <= 1'b0;
`ad16_CCtli2 <= 1'b0;
`ad16_CCtli3 <= 1'b0;
`ad16_CCtli4 <= 1'b0;
`ad16_CCtli5 <= 1'b0;
`ad16_CCtlEn <= 1'b0;
`ad16_CCtlLd <= 1'b1;
`ad16_RACReset <= 1'b1;
`ad16_ExtBE <= 1'b0;
`ad16_DelayIn <= 1'b1;
`ifdef GATE_LEVEL
force reality.rcp_0.tst_synclk_set = 0; repeat (64) @(posedge bus_clk);
release reality.rcp_0.tst_synclk_set;
`else
force reality.rcp_0.pad_0.left_pads.tst_synclk_set = 0; repeat (64) @(posedge bus_clk);
release reality.rcp_0.pad_0.left_pads.tst_synclk_set;
`endif
mask_ad16rw <= 1'b0;
ad16_data <= 'bz; repeat (16) @(posedge bus_clk);
repeat (4) @(posedge reality.rcp_0.mclock_pad);
// reset sequence
reset_l <= HIGH; repeat (4) @(posedge reality.rcp_0.mclock_pad);
reset_l <= LOW; repeat (60) @(posedge reality.rcp_0.mclock_pad);
reset_l <= HIGH;
end
endtask
task NormToMUX;
begin
test <= HIGH; repeat (4) @(posedge bus_clk);
reset_l <= HIGH; repeat (4) @(posedge bus_clk);
reset_l <= LOW; repeat (4) @(posedge bus_clk);
end
endtask
task NormToBYP;
begin
mask_ad16rw <= 1'b1;
reset_l <= LOW;
test <= LOW;
`ad16_ByPass <= 1'b1;
`ad16_SynClkSet <= 1'b0;
`ad16_BISTMode <= 1'b0;
`ad16_IOSTMode <= 1'b0;
`ad16_CCtli0 <= 1'b0;
`ad16_CCtli1 <= 1'b0;
`ad16_CCtli2 <= 1'b0;
`ad16_CCtli3 <= 1'b0;
`ad16_CCtli4 <= 1'b0;
`ad16_CCtli5 <= 1'b0;
`ad16_CCtlEn <= 1'b0;
`ad16_CCtlLd <= 1'b1;
`ad16_RACReset <= 1'b1;
`ad16_ExtBE <= 1'b0;
`ad16_DelayIn <= 1'b0; @(negedge bus_clk); repeat (2) @(posedge bus_clk);
test <= HIGH; repeat (1) @(posedge bus_clk);
reset_l <= HIGH; repeat (1) @(posedge bus_clk);
reset_l <= LOW; repeat (8) @(posedge bus_clk);
`ad16_SynClkSet <= 1'b1; repeat (7) @(posedge bus_clk);
reset_l <= HIGH; repeat (16) @(posedge bus_clk);
reset_l <= LOW; repeat (1) @(posedge bus_clk);
mask_ad16rw <= 1'b0;
ad16_data <= 'bz; repeat (240) @(posedge bus_clk);
reset_l <= HIGH;
end
endtask
task Norm_BYP_Norm;
begin
// to MUX
mask_ad16rw <= 1'b1;
test <= HIGH; repeat (4) @(posedge bus_clk);
reset_l <= HIGH; repeat (4) @(posedge bus_clk);
reset_l <= LOW; repeat (160) @(posedge bus_clk);
`ad16_SynClkSet <= 1'b1; repeat (16) @(posedge bus_clk);
reset_l <= HIGH; repeat (4) @(posedge bus_clk);
// mask_ad16rw <= 1'b0;
// to NORM
test <= LOW; repeat (4) @(posedge bus_clk);
reset_l <= LOW; repeat (4) @(posedge bus_clk);
mask_ad16rw <= 1'b0;
ad16_data <= 'bz; repeat (8) @(posedge bus_clk);
// reset sequence
reset_l <= HIGH; repeat (16) @(posedge bus_clk);
reset_l <= LOW; repeat (232) @(posedge bus_clk);
reset_l <= HIGH;
end
endtask
task RAC_BIST_TEST;
begin
mask_ad16rw <= 1'b1;
`ad16_ByPass <= 1'b0;
`ad16_SynClkSet <= 1'b0;
`ad16_BISTMode <= 1'b0;
`ad16_IOSTMode <= 1'b0;
`ad16_CCtli0 <= 1'b0;
`ad16_CCtli1 <= 1'b0;
`ad16_CCtli2 <= 1'b0;
`ad16_CCtli3 <= 1'b0;
`ad16_CCtli4 <= 1'b0;
`ad16_CCtli5 <= 1'b0;
`ad16_CCtlEn <= 1'b0;
`ad16_CCtlLd <= 1'b1;
`ad16_RACReset <= 1'b1;
`ad16_ExtBE <= 1'b0;
`ad16_DelayIn <= 1'b1; repeat (100) @(posedge bus_clk);
`ad16_SynClkSet <= 1'b1;
`ad16_RACReset <= 1'b1; repeat (100) @(posedge bus_clk);
`ad16_RACReset <= 1'b0; repeat (100) @(posedge bus_clk);
`ad16_CCtlLd <= 1'b0;
`ad16_RACReset <= 1'b1; repeat (100) @(posedge bus_clk);
fork
`ad16_BISTMode <= 1'b1; wait (`ad16_BISTFlag==0);
while ((wait_cnt < 'hfff) && (`ad16_BISTFlag !== 0))
begin
if (wait_cnt[4:0] == 'h0)
$display ($time," BISTFlag=%b, BISTFlag wait count = %d", `ad16_BISTFlag,wait_cnt);
@(posedge bus_clk) wait_cnt <= wait_cnt + 'h1;
if (wait_cnt == 'hff0)
begin
$display ($time," ERROR: BIST TimeOut");
$finish;
end
end
join
repeat (100) @(posedge bus_clk);
`ad16_BISTMode <= 1'b0; wait (`ad16_BISTFlag==1);
repeat (100) @(posedge bus_clk);
`ad16_RACReset <= 1'b1; repeat (100) @(posedge bus_clk);
end
endtask
task DELAY_TEST;
begin
mask_ad16rw <= 1'b1;
`ad16_DelayIn <= 1'b0; repeat (8) @(posedge bus_clk);
`ad16_DelayIn <= 1'b1; repeat (8) @(posedge bus_clk);
`ad16_DelayIn <= 1'b0; repeat (8) @(posedge bus_clk);
`ad16_DelayIn <= 1'b1; repeat (8) @(posedge bus_clk);
`ad16_DelayIn <= 1'b0; repeat (8) @(posedge bus_clk);
end
endtask
endmodule