module xbus_mon(clock, reset_l);

`include "rcp.vh"
`include "define.vh"

input clock;
input reset_l;

reg monitor;
initial monitor = $test$plusargs("xbus_mon");

always @(posedge clock) begin
	if (monitor && reset_l && reality.rcp_0.cbuf_write) begin
		$display(`CLOCK_COUNT, " : xbus   data - %h", reality.rcp_0.xbus_data);
		end
	end

endmodule