vclock.tcl 1.86 KB
#################################
# VIDEOCLK (MAX:~45MHz)         #
#################################


# Get delay from pllv/FO to *reg*/H02 ---------------------------

set vclock_latency_max 100000

   foreach_in_collection cur_path \
       [ get_timing_paths -nworst 10000 -max_paths 10000 \
         -from [get_pins pllv/FO] \
         -to   [get_pins *reg*/H02] \
         -delay max_rise \
       ] {
           set cur_delay [ get_attribute $cur_path arrival   ]
           set cur_end   [ get_attribute $cur_path endpoint  ]
           set cur_name  [ get_attribute $cur_end  full_name ]
           echo [ format "%s : %s" $cur_name $cur_delay ]
           if {$cur_delay < $vclock_latency_max} { set vclock_latency_max $cur_delay }
        
   }
   echo [ format "vclock_latency_max : %s" $vclock_latency_max ]


create_clock \
 -name VCLOCK \
 -period 19.6 \
 -waveform [ list [expr 0.0 - $vclock_latency_max] [expr 9.8 - $vclock_latency_max ] ] \
 [ get_pins pllv/FO ]

set_propagated_clock \
 [ get_clocks VCLOCK ]




#/*
# * digital video port;
# * synchronous output;
# * set output delay to 50% of cycle time to force flops close to pads;
# */


set_max_delay 2.0  -from VCLOCK -to PAD_VCLOCK

set_output_delay 10 -clock VCLOCK -max [get_ports PAD_VDATA*]
set_output_delay 10 -clock VCLOCK -max [get_ports PAD_VSYNC]
###set_output_delay 0.5 -clock VCLOCK -min [get_ports PAD_VDATA*]
###set_output_delay 0.5 -clock VCLOCK -min [get_ports PAD_VSYNC]


#/*
# * analog video port;
# * PAD_VOA, PAD_VOB, PAD_VOC do not need constraints;
# * the wires from DAC to pads are dont_touch above;
# */

#/*
# * audio port;
# * output synchronous to video clock;
# * set output delay to 50% of cycle time to force flops close to pads;
# */

set_output_delay 10 -clock VCLOCK -max [list PAD_ACLOCK PAD_ADATA PAD_AWORD]
###set_output_delay 0.5 -clock VCLOCK -min [list PAD_ACLOCK PAD_ADATA PAD_AWORD]