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#!/bin/csh -f
vcs \
-cc gcc \
+incdir+chip/include \
-Mupdate \
+vcs+lic+wait \
+cli+3 \
+libext+.v+ \
+sdfverbose \
-lX11 -notice \
-l out_vcscomp.log \
-o out_simv \
./test.v \
./bb_layout.v_0313 \
/netfas5/design/bbsoc/bblib/RevA/VR4300/current/NB4300V01_ver22b.vp \
/netfas5/design/bbsoc/bblib/RevA/VR4300/current/ABPLSSCH_cpu.vp \
/netfas5/design/bbsoc/bblib/RevA/PLL/current/ABPLSSCH_3.vp \
/netfas5/design/bbsoc/bblib/RevA/PLL/current/AAPLSVRH.vp \
/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvcp_nc15gfh/nvcp_nc15gfh.v \
/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvrm_nc15gfh_16x32/nvrm_nc15gfh_16x32.v \
/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvrm_nc15gfh_64x32/nvrm_nc15gfh_64x32.v \
-y /netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/CB12/cmos_1.5V/vcs/full_model/ABD3835BM \
-y /netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/verilog/BINV/ \
-y /netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/verilog/USB1 \
-y /netfas5/design/bbsoc/bblib/RevA/SRAM_ROM/current/lib/CB12/cmos_1.5V \
-y /opc/cb12_V3.1.0/solaris/lib/CB12/cmos_1.5V/vcs/full_model/analog \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/gating \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/nec_bscan \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/oscillator \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/scan \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/testact \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/clockdriver \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/iobuffer \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/nec_scan \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/primitive \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/special \
-y /opc/cb12_V3.1.0/solaris/lib/common/verilog/verilog_udp