// vr4300 behavioral bus model;
// unidirectional sysad;
// :set tabstop=4

`timescale 1ns/1ns

module NB4300V01 (
	MASTERCLOCK,
	DIVMODE2, DIVMODE1, DIVMODE0,
	COLDRESETB, RESETB,
	PLOCK,
	OSYSAD31, OSYSAD30, OSYSAD29, OSYSAD28, OSYSAD27, OSYSAD26, OSYSAD25, OSYSAD24,
	OSYSAD23, OSYSAD22, OSYSAD21, OSYSAD20, OSYSAD19, OSYSAD18, OSYSAD17, OSYSAD16,
	OSYSAD15, OSYSAD14, OSYSAD13, OSYSAD12, OSYSAD11, OSYSAD10, OSYSAD9, OSYSAD8,
	OSYSAD7, OSYSAD6, OSYSAD5, OSYSAD4, OSYSAD3, OSYSAD2, OSYSAD1, OSYSAD0,
	ISYSAD31, ISYSAD30, ISYSAD29, ISYSAD28, ISYSAD27, ISYSAD26, ISYSAD25, ISYSAD24,
	ISYSAD23, ISYSAD22, ISYSAD21, ISYSAD20, ISYSAD19, ISYSAD18, ISYSAD17, ISYSAD16,
	ISYSAD15, ISYSAD14, ISYSAD13, ISYSAD12, ISYSAD11, ISYSAD10, ISYSAD9, ISYSAD8,
	ISYSAD7, ISYSAD6, ISYSAD5, ISYSAD4, ISYSAD3, ISYSAD2, ISYSAD1, ISYSAD0,
	OSYSCMD4, OSYSCMD3, OSYSCMD2, OSYSCMD1, OSYSCMD0,
	ISYSCMD4, ISYSCMD3, ISYSCMD2, ISYSCMD1, ISYSCMD0,
	SYSEN, PVALIDB, PREQB, PMASTERB,
	EOKB, EVALIDB, EREQB,
	NMIB, INTB4, INTB3, INTB2, INTB1, INTB0,
	SI7, SI6, SI5, SI4, SI3, SI2, SI1, SI0,
	SO7, SO6, SO5, SO4, SO3, SO2, SO1, SO0,
	BUNRI, TEST, TEST1, TEST0,
	TBI51, TBI50,
	TBI49, TBI48, TBI47, TBI46, TBI45, TBI44, TBI43, TBI42, TBI41, TBI40,
	TBI39, TBI38, TBI37, TBI36, TBI35, TBI34, TBI33, TBI32, TBI31, TBI30,
	TBI29, TBI28, TBI27, TBI26, TBI25, TBI24, TBI23, TBI22, TBI21, TBI20,
	TBI19, TBI18, TBI17, TBI16, TBI15, TBI14, TBI13, TBI12, TBI11, TBI10,
	TBI9, TBI8, TBI7, TBI6, TBI5, TBI4, TBI3, TBI2, TBI1, TBI0,
	TBO39, TBO38, TBO37, TBO36, TBO35, TBO34, TBO33, TBO32, TBO31, TBO30,
	TBO29, TBO28, TBO27, TBO26, TBO25, TBO24, TBO23, TBO22, TBO21, TBO20,
	TBO19, TBO18, TBO17, TBO16, TBO15, TBO14, TBO13, TBO12, TBO11, TBO10,
	TBO9, TBO8, TBO7, TBO6, TBO5, TBO4, TBO3, TBO2, TBO1, TBO0,
	SCANSMC, SCANTMC,
	BYPASSPLLMODE, BYPASSPLLPCLK, BYPASSPLLSCLK,
	AVDD1, AGND1
);
	input MASTERCLOCK;
	input DIVMODE2, DIVMODE1, DIVMODE0;
	input COLDRESETB, RESETB;
	output PLOCK;
	output OSYSAD31, OSYSAD30, OSYSAD29, OSYSAD28, OSYSAD27, OSYSAD26, OSYSAD25, OSYSAD24;
	output OSYSAD23, OSYSAD22, OSYSAD21, OSYSAD20, OSYSAD19, OSYSAD18, OSYSAD17, OSYSAD16;
	output OSYSAD15, OSYSAD14, OSYSAD13, OSYSAD12, OSYSAD11, OSYSAD10, OSYSAD9, OSYSAD8;
	output OSYSAD7, OSYSAD6, OSYSAD5, OSYSAD4, OSYSAD3, OSYSAD2, OSYSAD1, OSYSAD0;
	input ISYSAD31, ISYSAD30, ISYSAD29, ISYSAD28, ISYSAD27, ISYSAD26, ISYSAD25, ISYSAD24;
	input ISYSAD23, ISYSAD22, ISYSAD21, ISYSAD20, ISYSAD19, ISYSAD18, ISYSAD17, ISYSAD16;
	input ISYSAD15, ISYSAD14, ISYSAD13, ISYSAD12, ISYSAD11, ISYSAD10, ISYSAD9, ISYSAD8;
	input ISYSAD7, ISYSAD6, ISYSAD5, ISYSAD4, ISYSAD3, ISYSAD2, ISYSAD1, ISYSAD0;
	output OSYSCMD4, OSYSCMD3, OSYSCMD2, OSYSCMD1, OSYSCMD0;
	input ISYSCMD4, ISYSCMD3, ISYSCMD2, ISYSCMD1, ISYSCMD0;
	output SYSEN, PVALIDB, PREQB, PMASTERB;
	input EOKB, EVALIDB, EREQB;
	input NMIB, INTB4, INTB3, INTB2, INTB1, INTB0;
	input SI7, SI6, SI5, SI4, SI3, SI2, SI1, SI0;
	output SO7, SO6, SO5, SO4, SO3, SO2, SO1, SO0;
	input BUNRI, TEST, TEST1, TEST0;
	input TBI51, TBI50;
	input TBI49, TBI48, TBI47, TBI46, TBI45, TBI44, TBI43, TBI42, TBI41, TBI40;
	input TBI39, TBI38, TBI37, TBI36, TBI35, TBI34, TBI33, TBI32, TBI31, TBI30;
	input TBI29, TBI28, TBI27, TBI26, TBI25, TBI24, TBI23, TBI22, TBI21, TBI20;
	input TBI19, TBI18, TBI17, TBI16, TBI15, TBI14, TBI13, TBI12, TBI11, TBI10;
	input TBI9, TBI8, TBI7, TBI6, TBI5, TBI4, TBI3, TBI2, TBI1, TBI0;
	output TBO39, TBO38, TBO37, TBO36, TBO35, TBO34, TBO33, TBO32, TBO31, TBO30;
	output TBO29, TBO28, TBO27, TBO26, TBO25, TBO24, TBO23, TBO22, TBO21, TBO20;
	output TBO19, TBO18, TBO17, TBO16, TBO15, TBO14, TBO13, TBO12, TBO11, TBO10;
	output TBO9, TBO8, TBO7, TBO6, TBO5, TBO4, TBO3, TBO2, TBO1, TBO0;
	input SCANSMC, SCANTMC;
	input BYPASSPLLMODE, BYPASSPLLPCLK, BYPASSPLLSCLK;
	input AVDD1, AGND1;

`include "rcp.vh"
`include "cpu.vh"
`include "define.vh"
`include "jctrl.vh"

	// set below defines to actual values of r4300 core;

`define	CPU_TCO		#2
`define	CPU_TSU		#2

	// cpu bus signals;
	// no sysad arbitration is used in the design;

	wire sysclk;					// sysad clock;
	wire [2:0] divmode;				// divider mode;
	wire coldrst_l;					// cold reset;
	wire warmrst_l;					// warm reset;
	wire [31:0] `CPU_TCO sysad_out;	// system addr/data bus;
	wire [31:0] sysad_in;			// system addr/data bus;
	wire [4:0] `CPU_TCO syscmd_out;	// system command bus;
	wire [4:0] syscmd_in;			// system command bus;
	wire `CPU_TCO pvalid_l;			// processor data valid;
	wire eok_l;						// external agent ready;
	wire evalid_l;					// external data valid;
	wire ereq_l;					// external request for bus interface;
	wire [4:0] int_l;				// cpu interrupts;
	wire nmi_l;						// non-maskable interrupt;

	assign sysclk = BYPASSPLLMODE? BYPASSPLLSCLK : MASTERCLOCK;
	assign divmode = { DIVMODE2, DIVMODE1, DIVMODE0 };
	assign coldrst_l = COLDRESETB;
	assign warmrst_l = RESETB;
	assign PLOCK = coldrst_l;

	assign {
		OSYSAD31, OSYSAD30, OSYSAD29, OSYSAD28, OSYSAD27, OSYSAD26, OSYSAD25, OSYSAD24,
		OSYSAD23, OSYSAD22, OSYSAD21, OSYSAD20, OSYSAD19, OSYSAD18, OSYSAD17, OSYSAD16,
		OSYSAD15, OSYSAD14, OSYSAD13, OSYSAD12, OSYSAD11, OSYSAD10, OSYSAD9, OSYSAD8,
		OSYSAD7, OSYSAD6, OSYSAD5, OSYSAD4, OSYSAD3, OSYSAD2, OSYSAD1, OSYSAD0 } = sysad_out;
	assign sysad_in = {
		ISYSAD31, ISYSAD30, ISYSAD29, ISYSAD28, ISYSAD27, ISYSAD26, ISYSAD25, ISYSAD24,
		ISYSAD23, ISYSAD22, ISYSAD21, ISYSAD20, ISYSAD19, ISYSAD18, ISYSAD17, ISYSAD16,
		ISYSAD15, ISYSAD14, ISYSAD13, ISYSAD12, ISYSAD11, ISYSAD10, ISYSAD9, ISYSAD8,
		ISYSAD7, ISYSAD6, ISYSAD5, ISYSAD4, ISYSAD3, ISYSAD2, ISYSAD1, ISYSAD0 };
	assign { OSYSCMD4, OSYSCMD3, OSYSCMD2, OSYSCMD1, OSYSCMD0 } = syscmd_out;
	assign syscmd_in = { ISYSCMD4, ISYSCMD3, ISYSCMD2, ISYSCMD1, ISYSCMD0 };

	assign SYSEN = 1'bx;			// not used;
	assign PVALIDB = pvalid_l;
	assign PREQB = 1'bx;			// not used;
	assign PMASTERB = 1'bx;			// not used;
	assign eok_l = EOKB;
	assign evalid_l = EVALIDB;
	assign ereq_l = EREQB;
	assign int_l = { INTB4, INTB3, INTB2, INTB1, INTB0 };
	assign nmi_l = NMIB;

	// declare wires with delays;
	// simulates t[co] and t[su];

	wire `CPU_TSU eok;
	wire [31:0] `CPU_TSU sysad;
	wire [4:0] `CPU_TSU syscmd;
	wire `CPU_TSU evalid;

	assign eok = eok_l;
	assign sysad = sysad_in;
	assign syscmd = syscmd_in;
	assign evalid = evalid_l;

	// internal variables;

	reg test_selected;

	// global cpu state;

	wire reset_l;			// cpu reset;
	reg ready;				// cpu is ready;
	reg slave;				// bus interface in slave mode;
	integer word;			// nth read word;
	integer nwords;			// # of words expected;
	integer rsp_timeout;	// repsonse timeout;

	assign reset_l = coldrst_l & warmrst_l;

	initial
	begin
		ready = 0;
		slave = 0;
		word = 0;
		nwords = 0;
		rsp_timeout = `CPU_RSP_TIMEOUT;
	end

	// register all cpu inputs;

	reg [31:0] r_sysad_out;
	reg [4:0] r_syscmd_out;
	reg r_pvalid_l;
	reg r_eok;
	reg rsp;

	assign sysad_out = r_sysad_out;
	assign syscmd_out = r_syscmd_out;
	assign pvalid_l = r_pvalid_l;

	always @(posedge sysclk)
	begin
		r_eok <= ~eok;
		rsp <= ~evalid & ~syscmd[3];
		if(rsp)
			slave <= 0;
	end

	// slave state machine;

	reg [31:0] data [0:7];		// read/write data buffer;
	reg data_err;				// response error bit was set;
	integer rsp_timer;			// read response timer;

	always @(posedge sysclk)
	begin
		if(evalid == 1'b0) begin
			if(slave !== 1'b1)
				$display("ERROR: %t: %M: evalid when not in slave state", $time);
			casex(syscmd)
				// read response;
				5'b1000x,
				5'b1100x,
				5'b1001x,
				5'b1101x: begin
					if(word >= nwords)
						$display("ERROR: %t: %M: excessive read response data", $time);
					if(word == 0)
						data_err = syscmd[1];
					data[word] = sysad;
					word = word + 1;
				end

				// all others are illegal;
				default:
					$display("ERROR: %t: %M: illegal syscmd %b", $time, syscmd);
			endcase
		end

		// timeout out read response;

		if(slave) begin
			rsp_timer = rsp_timer + 1;
			if(rsp_timer > rsp_timeout) begin
				$display("ERROR: %t: %M: read response timeout", $time);
				$finish;
			end
		end else begin
			rsp_timer = 0;
			word = 0;
		end
	end

	// cpu ready flag and assertions;

	always @(posedge sysclk)
	begin
		if((reset_l === 0) | (reset_l === 1))
			ready = reset_l;
		if(ready) begin
			if((r_pvalid_l === 'bx) | (r_pvalid_l === 'bz))
				$display("ERROR: %t: %M: pvalid_l is %b", $time, r_pvalid_l);
			if((ereq_l === 'bx) | (ereq_l === 'bz))
				$display("ERROR: %t: %M: ereq_l is %b", $time, ereq_l);
			if((eok === 'bx) | (eok === 'bz))
				$display("ERROR: %t: %M: eok_l is %b", $time, eok);
			if((evalid === 'bx) | (evalid === 'bz))
				$display("ERROR: %t: %M: evalid_l is %b", $time, evalid);
		end
	end

	// reset is asynchronous;

	always @(reset_l)
	begin
		if(reset_l === 1'b0) begin
			assign r_pvalid_l = 1;
			slave = 0;
			word = 0;
			nwords = 0;
		end else if(reset_l === 1'b1)
			deassign r_pvalid_l;
		else
			$display("ERROR: %t: %M: reset_l %b", $time, reset_l);
	end

	// wait for cpu to come out of reset;

	task wait_out_of_reset;
		begin
			@(posedge ready);
			@(posedge sysclk);
		end
	endtask

	// cpu bus interface tasks;

	task wait_eok;
		integer rdycnt;
		begin
			rdycnt = 0;
			while(r_eok !== 1) begin
				@(posedge sysclk);
				if(rdycnt >= `CPU_RDY_TIMEOUT) begin
					$display("ERROR: %t: %M: timeout", $time);
					$finish;
				end
				rdycnt = rdycnt + 1;
			end
			// XXX pmaster
		end
	endtask

	// single write request;
	// req[1:0] is write size;

	task swrite;
		input [31:0] addr;		// physical address;
		input [1:0] size;		// request size;
		input [31:0] wdata;		// write data;
		begin
			// output address, cmd and pvalid;
			// wait for eok;

			r_pvalid_l = 0;
			r_sysad_out = addr;
			r_syscmd_out = { 3'b010, size };
			@(posedge sysclk);
			wait_eok;

			// single writes have only one data phase;

			r_sysad_out = wdata;
			r_syscmd_out = 5'b10000;
			@(posedge sysclk);

			// eok can cancel bus request;
			// spin until successfully issued;

			while(r_eok !== 1) begin
				r_sysad_out = addr;
				r_syscmd_out = { 3'b010, size };
				@(posedge sysclk);
				wait_eok;

				r_sysad_out = wdata;
				r_syscmd_out = 5'b10000;
				@(posedge sysclk);
			end

			// deassert pvalid;
			// drive Xs on sysad;

			r_pvalid_l = 1;
			r_sysad_out = 'bx;
			r_syscmd_out = 'bx;
		end
	endtask

	// single read request;

	task sread;
		input [31:0] addr;		// phys address;
		input [1:0] size;		// single size;
		output [31:0] rdata;	// read data;
		begin
			// output address, cmd and pvalid;
			// wait for eok;

			r_pvalid_l = 0;
			r_sysad_out = addr;
			r_syscmd_out = { 3'b000, size };
			@(posedge sysclk);
			wait_eok;

			// tri-state sysad after address phase;

			nwords = 1;
			r_pvalid_l = 1;
			r_sysad_out = 'bx;
			r_syscmd_out = 'bx;
			@(posedge sysclk);
			slave = 1;

			// eok can cancel bus request;
			// spin until successfully issued;

			while(r_eok !== 1) begin
				slave = 0;
				r_pvalid_l = 0;
				r_sysad_out = addr;
				r_syscmd_out = { 3'b000, size };
				@(posedge sysclk);
				wait_eok;

				r_pvalid_l = 1;
				r_sysad_out = 'bx;
				r_syscmd_out = 'bx;
				@(posedge sysclk);
				slave = 1;
			end

			// wait for read response;
			// return mastership of sysad to cpu;

			@(negedge slave);
			rdata = data[0];
		end
	endtask

	// block write request;
	// issued for cache line write-back;
	// target can only be main memory;

	task bwrite;
		input [31:0] addr;		// physical address;
		input [1:0] size;		// block size;
		integer i;
		begin
			// output address, cmd and pvalid;
			// wait for eok;

			r_pvalid_l = 0;
			r_sysad_out = addr;
			r_syscmd_out = { 3'b011, size };
			@(posedge sysclk);
			wait_eok;

			// block writes have a fixed data size;
			// write data pattern is ADD or ADDDDDDDD;

			r_sysad_out = data[0];
			r_syscmd_out = 5'b11000;
			@(posedge sysclk);

			// eok can cancel bus request;
			// spin until successfully issued;

			while(r_eok !== 1) begin
				r_sysad_out = addr;
				r_syscmd_out = { 3'b011, size };
				@(posedge sysclk);
				wait_eok;

				r_sysad_out = data[0];
				r_syscmd_out = 5'b11000;
				@(posedge sysclk);
			end

			// finish sending the data;

			for(i = 1; i < (2 << size[1:0]) - 1; i = i + 1) begin
				r_sysad_out = data[i];
				@(posedge sysclk);
			end

			// send last data item;

			r_sysad_out = data[i];
			r_syscmd_out = 5'b10000;
			@(posedge sysclk);

			r_pvalid_l = 1;
			r_sysad_out = 'bx;
			r_syscmd_out = 'bx;
		end
	endtask

	// cpu block read;
	// issued to fill icache or dcache;
	// target can only be main memory, no io devices support block requests;

	task bread;
		input [31:0] addr;		// physical address;
		input [1:0] size;		// block size;
		integer i;
		begin
			// output address, cmd and pvalid;
			// wait for eok;

			r_pvalid_l = 0;
			r_sysad_out = addr;
			r_syscmd_out = { 3'b001, size };
			@(posedge sysclk);
			wait_eok;

			// tri-state sysad after address phase;

			case(size)
				2'b00: nwords = 2;
				2'b01: nwords = 4;
				2'b10: nwords = 8;
				2'b11: $display("ERROR: %t: %M: illegal block size %b", $time, size);
			endcase
			r_pvalid_l = 1;
			r_sysad_out = 'bx;
			r_syscmd_out = 'bx;
			@(posedge sysclk);
			slave = 1;

			// eok can cancel bus request;
			// spin until successfully issued;

			while(r_eok !== 1) begin
				slave = 0;
				r_pvalid_l = 0;
				r_sysad_out = addr;
				r_syscmd_out = { 3'b001, size };
				@(posedge sysclk);
				wait_eok;

				r_pvalid_l = 1;
				r_sysad_out = 'bx;
				r_syscmd_out = 'bx;
				@(posedge sysclk);
			end

			// wait for read response;
			// return mastership of sysad to cpu;

			@(negedge slave);
		end
	endtask

	// put random delay between bus requests;

	task req_spacing;
		input [2:0] delay;
		begin
			repeat(delay) @(posedge sysclk);
		end
	endtask

	// make valid byte address for single size;

	function [1:0] sgl_addr;
		input [1:0] size;		// request size;
		reg [1:0] addr;			// valid low-order address bits;
		begin
			case(size)
				2'b00: addr = $random;			// byte;
				2'b01: addr = $random & 2'b10;	// 16-bit word;
				2'b10: addr = $random & 2'b01;	// tri-byte;
				2'b11: addr = 2'b00;			// 32-bit word;
			endcase
			sgl_addr = addr;
		end
	endfunction

	// check read data;

	task rd_check;
		input [2:0] word;		// word to check;
		input [31:0] exp;		// expected data;
		input [31:0] mask;		// compare mask;
		input err;				// extected error;
		begin
			if(mask == 32'h0)
				$display("ERROR: %t: %M: mask of 0", $time);
			if(((data[word] & mask) !== (exp & mask)) | (err !== data_err)) begin
				$display("ERROR: %t: %M: data[%1d] mask 0x%h miscompare 0x%h/%b exp 0x%h/%b",
					$time, word, mask, data[word], data_err, exp, err);
			end
		end
	endtask

	// check bus error;

	task berr_check;
		input err;				// extected error;
		begin
			if(data_err !== err)
				$display("ERROR: %t: %M: bus error %b exp %b", $time, data_err, err);
		end
	endtask

	// make valid word address for block size;
	// block addresses are always double-word aligned;

	function [4:2] blk_addr;
		input [1:0] size;		// request size;
		reg [4:2] mask;			// valid low-order address bits;
		reg [4:2] addr;			// valid low-order address bits;
		begin
			case(size)
				2'b00: mask = 3'b110;
				2'b01: mask = 3'b100;
				2'b10: mask = 3'b000;
				2'b11: $display("ERROR: %t: %M: illegal blk size %b", $time, size);
			endcase
			blk_addr = $random & mask;
		end
	endfunction

	// make valid subblock order address for block size;

	function [4:2] sbo_addr;
		input [1:0] size;		// request size;
		reg [4:2] sbo;			// sub-block order;
		begin
			case(size)
				2'b00: sbo = 3'b000;
				2'b01: sbo = 3'b010;
				2'b10: sbo = 3'b110;
				2'b11: $display("ERROR: %t: %M: illegal blk size %b", $time, size);
			endcase
			sbo_addr = $random & sbo;
		end
	endfunction

	// get a random memory address;
	// consider memory spaces and existing size;
	// make sure requested block does not wrap;
	// enforce alignment;

	function [31:0] rand_mem_addr;
		input [31:24] space;	// memory space;
		input [23:0] size;		// size of block;
		input [23:0] align;		// alignment;
		reg [31:0] mask;		// address mask;
		reg [31:0] addr;		// address;
		reg [31:0] base;		// base of space;
		begin
			mask = vsim.MEM_SIZE - 1;
			if(space[31:24] == 8'd0) begin
				mask = mask >> 1;
				mask[31:24] = 8'd0;
				base = 32'h0000_0000;
			end else if(space[31:24] < 8'd2) begin
				mask[31:23] = 7'd0;
				base = 32'h0100_0000;
			end else if(space[31:30] == 2'b10)
				base = 32'h8000_0000;
			else begin
				base = 32'bx;
				$display("ERROR: %t: %M: space 0x%h", $time, space);
			end
			addr = $random & mask;
			while((addr + size) > mask)
				addr = $random & mask;
			rand_mem_addr = base | (addr & ~(align - 1));
		end
	endfunction

	// setup block data pattern;
	// use inverted, byte and bit swapped initial;

	task blk_data;
		input [31:0] word;
		integer n;
		reg [31:0] swap;
		begin
			for(n = 0; n < 32; n = n + 1)
				swap[n] = word[31 - n];
			data[0] = word;
			data[1] = ~data[0];
			data[2] = { word[15:0], word[31:16] };
			data[3] = ~data[2];
			data[4] = { word[23:16], word[31:24], word[7:0], word[15:8] };
			data[5] = ~data[4];
			data[6] = swap;
			data[7] = ~data[6];
		end
	endtask

	// check block read data;

	task blk_check;
		input [1:0] size;		// request size;
		input [31:0] exp;		// expected data;
		input err;				// extected error;
		input [2:0] sbo;		// subblock order;
		reg [31:0] pxe;			// exp bits backwards;
		reg [31:0] word [0:7];	// expected word of burst;
		integer n;
		begin
			if(size == `CPU_SIZE_RSVD)
				$display("ERROR: %t: %M: blk size %b", $time, size);
			word[0] = exp;
			word[1] = ~word[0];
			word[2] = { exp[15:0], exp[31:16] };
			word[3] = ~word[2];
			if(size == `CPU_SIZE_32) begin
				word[4] = { exp[23:16], exp[31:24], exp[7:0], exp[15:8] };
				word[5] = ~word[4];
				for(n = 0; n < 32; n = n + 1)
					pxe[n] = exp[31 - n];
				word[6] = pxe;
				word[7] = ~pxe;
			end

			rd_check(0, word[0 ^ sbo], 32'hffffffff, err);
			rd_check(1, word[1 ^ sbo], 32'hffffffff, err);
			if((size == `CPU_SIZE_16) | (size == `CPU_SIZE_32)) begin
				rd_check(2, word[2 ^ sbo], 32'hffffffff, err);
				rd_check(3, word[3 ^ sbo], 32'hffffffff, err);
			end
			if(size == `CPU_SIZE_32) begin
				rd_check(4, word[4 ^ sbo], 32'hffffffff, err);
				rd_check(5, word[5 ^ sbo], 32'hffffffff, err);
				rd_check(6, word[6 ^ sbo], 32'hffffffff, err);
				rd_check(7, word[7 ^ sbo], 32'hffffffff, err);
			end
		end
	endtask

	// test all r/w bits in a register;
	// test asumes no register side effects;

	task test_reg;
		input [31:0] addr;		// register address;
		input [31:0] mask;		// bits to test;
		input [31:0] zero;		// 0 and mask;
		input [31:0] one;		// 1 or mask;
		reg [31:0] wdata;		// write data;
		reg [31:0] rdata;		// read data;
		integer n;
		begin
			$display("test: %M: reg 0x%h mask 0x%h", addr, mask);
			if(mask & (~zero | one)) begin
				$display("ERROR: %t: %M: mask %h zero %h one %h discrepancy",
					$time, mask, zero, one);
			end
			for(n = 0; n < 32; n = n + 1) begin
				wdata = (1 << n);
				if(mask & wdata) begin
					wdata = (wdata & zero) | one;
					swrite(addr, `CPU_SIZE_4, wdata);
					sread(addr, `CPU_SIZE_4, rdata);
					if(rdata[n] !== wdata[n]) begin
						$display("ERROR: %t: %M: reg 0x%x bit %0d mismatch, %b exp %b",
							$time, addr, n, rdata[n], wdata[n]);
					end
				end
			end
		end
	endtask


	// the simulator is build with either the ipc interface or the verilog tests;
	// both should not coexist because there is no synchronization between them;
	// include various tasks used by both ipc and verilog tests;

`include "tasks/mem_tasks.v"

`ifdef	IPC
`else	// IPC
`include "test.v"
`endif	// IPC

endmodule