test_adac.v
1.22 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
// a fake dac - uses $display to output audio data
module test_adac ( i, j, abus_data, abus_clock, abus_word );
// input [15:0] i;
input i; // reset when i == 0
input [31:0] j; // another test output parameter
input abus_data; // audio data
input abus_clock; // audio transmit clock
input abus_word; // audio high word flag
reg [15:0] left;
reg [15:0] right;
reg last_word;
integer count;
wire [15:0] left_temp;
wire [15:0] right_temp;
reg [63:0] mytime;
assign left_temp[15:0] = { left[14:0], abus_data };
assign right_temp[15:0] = { right[14:0], abus_data };
reg monitor;
initial monitor = $test$plusargs("adac_mon");
always @(i) begin
if (i == 0) count = 0;
end
always @(posedge abus_clock) begin
if (monitor) begin
if (last_word == 0 && abus_word == 1) begin // rising abus_word
mytime = $time;
$display("audio %d %d %3d left %h right %h output ",
i, mytime[20:0], count, left, right);
count = count + 1;
end
if (abus_word == 1) left = left_temp;
if (abus_word == 0) right = right_temp;
last_word = abus_word;
end
end
endmodule // testdac