usb_tests.v
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// :set tabstop=4
// USB external host test module
module usb_tests(
usb_dminus,
usb_dplus,
usb_dp_high,
usb_d_low_n,
usb_vbus_vld,
usb_id,
usb_vbus_on
);
inout [1:0] usb_dminus; // D-
inout [1:0] usb_dplus; // D+
input [1:0] usb_dp_high; // pullup resistor
input [1:0] usb_d_low_n;
output [1:0] usb_vbus_vld;
output [1:0] usb_id;
input [1:0] usb_vbus_on;
wire [1:0] usbxr_oen;
`ifdef SIMGATE
assign usbxr_oen[0] = vsim.bb.usbxr_oen_0_;
assign usbxr_oen[1] = vsim.bb.usbxr_oen_1_;
`else // SIMGATE
assign usbxr_oen = vsim.bb.usbxr_oen;
`endif // SIMGATE
ext_host_ctl ext_host_ctl0(
.usb_dminus(usb_dminus[0]),
.usb_dplus(usb_dplus[0]),
.usb_dp_high(usb_dp_high[0]),
.usb_d_low_n(usb_d_low_n[0]),
.usb_vbus_vld(usb_vbus_vld[0]),
.usb_id(usb_id[0]),
.usb_vbus_on(usb_vbus_on[0]),
.usbxr_oen(usbxr_oen[0]));
ext_host_ctl ext_host_ctl1(
.usb_dminus(usb_dminus[1]),
.usb_dplus(usb_dplus[1]),
.usb_dp_high(usb_dp_high[1]),
.usb_d_low_n(usb_d_low_n[1]),
.usb_vbus_vld(usb_vbus_vld[1]),
.usb_id(usb_id[1]),
.usb_vbus_on(usb_vbus_on[1]),
.usbxr_oen(usbxr_oen[1]));
endmodule //module usb_tests