video_tasks.v
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task vi_test;
// test debug socket
begin
test_selected <= HIGH;
repeat (10) @(posedge sysclk);
mem_config;
// put some data in the dram first
// swrite(BUS_ADDRESS_DRAM, 3, 32'h0ad00da0);
// swrite(BUS_ADDRESS_DRAM+4, 3, 32'h1ad11da1);
// swrite(BUS_ADDRESS_DRAM+8, 3, 32'h2ad22da2);
// swrite(BUS_ADDRESS_DRAM+12, 3, 32'h3ad33da3);
// swrite(BUS_ADDRESS_DRAM+16, 3, 32'h4ad44da4);
// write registers in video controller
sread(BUS_ADDRESS_VI_CTRL, 3, data[0]);
if (data[0] !== 32'h00000000)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_ORIGIN, 3, 32'h00001000);
sread(BUS_ADDRESS_VI_ORIGIN, 3, data[0]);
if (data[0] !== 32'h00001000)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_WIDTH, 3, 32'h00000400);
sread(BUS_ADDRESS_VI_WIDTH, 3, data[0]);
if (data[0] !== 32'h00000400)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_V_INT, 3, 32'h000003FF);
sread(BUS_ADDRESS_VI_V_INT, 3, data[0]);
if (data[0] !== 32'h000003FF)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_BURST, 3, 32'h00820404);
sread(BUS_ADDRESS_VI_BURST, 3, data[0]);
if (data[0] !== 32'h00820404)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_V_SYNC, 3, 32'h00000010);
sread(BUS_ADDRESS_VI_V_SYNC, 3, data[0]);
if (data[0] !== 32'h00000010)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_H_SYNC, 3, 32'h00000100);
sread(BUS_ADDRESS_VI_H_SYNC, 3, data[0]);
if (data[0] !== 32'h00000100)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_LEAP, 3, 32'h01000100);
sread(BUS_ADDRESS_VI_LEAP, 3, data[0]);
if (data[0] !== 32'h01000100)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_H_START, 3, 32'h00200040);
sread(BUS_ADDRESS_VI_H_START, 3, data[0]);
if (data[0] !== 32'h00200040)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_V_START, 3, 32'h0005000D);
sread(BUS_ADDRESS_VI_V_START, 3, data[0]);
if (data[0] !== 32'h0005000D)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_V_BURST, 3, 32'h0005000D);
sread(BUS_ADDRESS_VI_V_BURST, 3, data[0]);
if (data[0] !== 32'h0005000D)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_X_SCALE, 3, 32'h00000400);
sread(BUS_ADDRESS_VI_X_SCALE, 3, data[0]);
if (data[0] !== 32'h00000400)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_Y_SCALE, 3, 32'h00000200);
sread(BUS_ADDRESS_VI_Y_SCALE, 3, data[0]);
if (data[0] !== 32'h00000200)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_CTRL, 3, 32'h0000015E);
sread(BUS_ADDRESS_VI_CTRL, 3, data[0]);
if (data[0] !== 32'h0000015E)
$display ("ERROR task vi_test read data is %h ",data[0]);
swrite(BUS_ADDRESS_VI_V_CURRENT, 3, 32'h00000000); // clr int
sread(BUS_ADDRESS_VI_V_CURRENT, 3, data[0]); // need some read
// wait for a while and watch dma
repeat (6000) @(posedge sysclk);
sread(BUS_ADDRESS_VI_V_CURRENT, 3, data[0]);
// while (data[0]) begin
// sread(BUS_ADDRESS_SI_STATUS, 3, data[0]);
// end
// dma status (data[0]) is done, so read data from dram
$finish;
end
endtask