// vsim.v v1 Frank Berndt
// top level dbx verilog simulation;
// :set tabstop=4

`timescale 1ns/1ns

module vsim;

	// clock generator;
	// create 50Mhz external clock;

`define	CLK_PERIOD	20		// clock period;
`define	N_VCCCLKS	128		// # of clocks for VCCOK=0;
`define TCO 		#2

	reg clkrun;				// clock running;
	reg CLK;				// external clock;
	reg GSR;				// global set/reset;
	reg GTS;				// global tri-state;

	assign glbl.GSR = GSR;
	assign glbl.GTS = GTS;

	initial
	begin
		CLK = 0;
		GSR = 1;			// global set&reset;
		GTS = 1;			// global tri-state;
		clkrun = 0;
		#50;
		clkrun = 1;
		repeat(`N_VCCCLKS) @(negedge CLK);
		GSR = 0;
		GTS = 0;			// release globals;
		@(posedge CLK);
	end

	always
		#(`CLK_PERIOD / 2) CLK = clkrun & ~CLK;

	// config interface;

	wire RST;				// pp reset;
	wire DONE;				// fpga is configured;
	wire SW;				// config switch;

	assign SW = 1'b0;		// debug mode;

	// parallel port interface;

	wire [7:0] DATA;		// data bus;
	wire ASTROBE;			// address strobe;
	wire DSTROBE;			// data strobe;
	wire WRITE;				// write to dbx;
	wire WAIT;				// wait;
	wire IRQ;				// interrupt to host;
	wire USR1;				// use signal 1;
	wire USR3;				// use signal 3;

	pullup ( ASTROBE );
	pullup ( DSTROBE );
	pullup ( WRITE );
	pullup ( WAIT );
	pullup ( IRQ );
	pullup ( USR1 );
	pullup ( USR3 );

	// bb IO interface;

	wire IORST;				// io bus reset;
	wire [15:0] IOAD;		// io addr/data bus;
	wire IOALE;				// address latch enable;
	wire IOR;				// read strobe;
	wire IOW;				// write strobe;
	wire IOCS0;				// io cs 0, debug port;
	wire IOCS2;				// io cs 2, button smapling;
	wire IOIRQ;				// interrupt to bb;

	pulldown ( IORST );
	pulldown ( IOALE );
	pullup ( IOW );
	pullup ( IOR );
	pullup ( IOCS0 );
	pullup ( IOCS2 );
	pullup ( IOIRQ );

	// button interface;

	wire BUT_A;				// button A;
	wire BUT_B;				// button B;
	wire BUT_C;				// button C;
	wire BUT_D;				// button D;
	wire BUT_E;				// button E;
	wire BUT_F;				// button F;
	wire BUT_L;				// button L;
	wire BUT_R;				// button R;
	wire BUT_Z;				// button Z;
	wire BUT_LEFT;			// button LEFT;
	wire BUT_RIGHT;			// button RIGHT;
	wire BUT_UP;			// button UP;
	wire BUT_DOWN;			// button DOWN;
	wire BUT_START;			// button START;

	// instantiate debug fpga;

	dbx dbx (
		.CLK(CLK),
		.SW(SW),
		.DATA(DATA),
		.ASTROBE(ASTROBE),
		.DSTROBE(DSTROBE),
		.WRITE(WRITE),
		.WAIT(WAIT),
		.IRQ(IRQ),
		.USR1(USR1),
		.USR3(USR3),
		.IORST(IORST),
		.IOAD(IOAD),
		.IOALE(IOALE),
		.IOR(IOR),
		.IOW(IOW),
		.IOCS0(IOCS0),
		.IOCS2(IOCS2),
		.IOIRQ(IOIRQ),
		.BUT_A(BUT_A),
		.BUT_B(BUT_B),
		.BUT_C(BUT_C),
		.BUT_D(BUT_D),
		.BUT_E(BUT_E),
		.BUT_F(BUT_F),
		.BUT_L(BUT_L),
		.BUT_R(BUT_R),
		.BUT_Z(BUT_Z),
		.BUT_LEFT(BUT_LEFT),
		.BUT_RIGHT(BUT_RIGHT),
		.BUT_UP(BUT_UP),
		.BUT_DOWN(BUT_DOWN),
		.BUT_START(BUT_START)
	);

	// pp interface;

	reg [7:0] pp_data;		// data bits;
	reg pp_oe;				// write to parallel port;
	reg pp_write;			// read/write signal;
	reg pp_astb;			// address strobe;
	reg pp_dstb;			// data strobe;

	initial
	begin
		pp_oe = 1'b0;		// do not drive bus;
		pp_write = 1'b0;	// read is default;
		pp_astb = 1'b0;		// no strobe;
		pp_dstb = 1'b0;		// no strobe;
	end

	assign WRITE = ~pp_write;
	assign ASTROBE = ~pp_astb;
	assign DSTROBE = ~pp_dstb;
	assign DATA = pp_oe? pp_data : 8'bz;

	// pp read/write cycle;

	task pp_rw;
		input write;		// read=0 write=1 cycle;
		input ad;			// addr=0 data=1 cycle;
		inout [7:0] data;	// data byte;
		begin
			wait(WAIT === 1'b0);
			#15;
			pp_write = write;
			pp_data = data;
			if(write)
				pp_oe = 1;
			#20;
			if(ad == 1'b0)
				pp_astb = 1'b1;
			else
				pp_dstb = 1'b1;
			#100;
			wait(WAIT === 1'b1);
			#200;
			data = DATA;
			pp_astb = 1'b0;
			pp_dstb = 1'b0;
			#20;
			pp_oe = 1'b0;
			pp_write = 1'b0;
			#50;
		end
	endtask

	// ide interface;

	reg io_rst;				// ide bus reset;
	reg [15:0] io_ad;		// addr/data bus;
	reg io_oe;				// drive io bus;
	reg io_ale;				// address latch enable;
	reg io_ior;				// read strobe;
	reg io_iow;				// write strobe;
	reg io_cs0;				// chip select 0;
	reg io_cs2;				// chip select 2;

	initial
	begin
		io_rst = 1'b0;		// reset by default;
		io_ad = 16'd0;
		io_oe = 1'b1;
		io_ale = 1'b0;
		io_ior = 1'b0;
		io_iow = 1'b0;
		io_cs0 = 1'b0;
		io_cs2 = 1'b0;
	end

	assign IORST = io_rst;
	assign IOAD = io_oe? io_ad : 16'bz;
	assign IOALE = io_ale;
	assign IOR = ~io_ior;
	assign IOW = ~io_iow;
	assign IOCS0 = ~io_cs0;
	assign IOCS2 = ~io_cs2;

	// ide read/write cycle;

	task ide_rw;
		input write;		// read=0 write=1 cycle;
		input cs2;			// use cs 2;
		input [15:0] addr;	// bus address;
		inout [15:0] data;	// r/w data;
		begin
			#10;
			io_ad = addr;
			io_ale = 1'b1;
			#20;
			io_ale = 1'b0;
			#10;
			io_ad = 16'bx;
			#10;
			if(write)
				io_ad = data;
			else
				io_oe = 1'b0;
			if(cs2)
				io_cs2 = 1'b1;
			else
				io_cs0 = 1'b1;
			#25;
			if(write)
				io_iow = 1'b1;
			else
				io_ior = 1'b1;
			#40;
			if(write == 1'b0)
				data = IOAD;
			io_iow = 1'b0;
			io_ior = 1'b0;
			#15;
			io_cs0 = 1'b0;
			io_cs2 = 1'b0;
			#10;
			io_ad = 16'd0;
			io_oe = 1'b1;
		end
	endtask

	// simulation tests;
	// run a few read writes on boths sides;
	// dump all the logic;

	reg [7:0] pp_cmd, pp_exp;
	reg [15:0] ide_cmd, ide_exp;
	integer n;

	initial
	begin
		$dumpvars(0, vsim);

		// test pp reset;
		// clears write & read pointers;
		// read and check status;

		$display("test: pp reset");
		pp_cmd = 8'b0100_0000;
		pp_rw(1, 0, pp_cmd);
		pp_rw(0, 0, pp_cmd);
		if(pp_cmd !== 8'd0)
			$display("ERROR: %t: %M: pp sts %b not 0", $time, pp_cmd);

		// test ide reset;
		// take bus out of reset;
		// read and check status;

		$display("test: ide reset");
		io_rst = 1'b1;
		ide_cmd = 16'b0100_0000;
		ide_rw(1, 0, 16'h4000, ide_cmd);
		ide_rw(0, 0, 16'h4000, ide_cmd);
		ide_exp = 16'd0;
		if(ide_cmd !== 16'd0)
			$display("ERROR: %t: %M: ide sts %b not 0", $time, ide_exp);

		// write entire buffer;

		$display("test: pp writes");
		for(n = 0; n < 2048; n = n + 1) begin
			pp_cmd = n[7:0] + n[15:8];
			pp_rw(1, 1, pp_cmd);
		end

		// read entire buffer;

		$display("test: pp reads");
		for(n = 0; n < 2048; n = n + 1) begin
			pp_rw(0, 1, pp_cmd);
			pp_exp = n[7:0] + n[15:8];
			if(pp_cmd !== pp_exp)
				$display("ERROR: %t: %M: pp read[%0d] 0x%x exp 0x%x", $time, n, pp_cmd, pp_exp);
		end

		// write entire buffer;

		$display("test: ide writes");
		for(n = 0; n < 1024; n = n + 1) begin
			ide_cmd = n;
			ide_rw(1, 0, n, ide_cmd);
		end

		// read entire buffer;

		$display("test: ide reads");
		for(n = 0; n < 1024; n = n + 1) begin
			ide_rw(0, 0, n, ide_cmd);
			if(ide_cmd !== n)
				$display("ERROR: %t: %M: ide read[%0d] 0x%x exp 0x%x", $time, n, ide_cmd, n[15:0]);
		end

		// send request host->bb;

		pp_cmd = 8'b0000_0001;
		pp_rw(1, 0, pp_cmd);
		pp_rw(0, 0, pp_cmd);
		pp_exp = 8'b0000_0001;
		if(pp_cmd !== pp_exp)
			$display("ERROR: %t: %M: pp[1] sts %b exp %b", $time, pp_cmd, pp_exp);

		// check that ide sees req & intr;

		ide_rw(0, 0, 16'h4000, ide_cmd);
		ide_exp = 16'b0000_0100;
		if(ide_cmd !== ide_exp)
			$display("ERROR: %t: %M: ide[2] sts %b exp %b", $time, ide_cmd, ide_exp);
		if(IOIRQ !== 1'b1)
			$display("ERROR: %t: %M: ide[3] irq %b exp 1", $time, IOIRQ);

		// send request host<-bb;

		ide_cmd = 8'b0000_0001;
		ide_rw(1, 0, 16'h4000, ide_cmd);
		ide_rw(0, 0, 16'h4000, ide_cmd);
		ide_exp = 16'b0000_0101;
		if(ide_cmd !== ide_exp)
			$display("ERROR: %t: %M: ide[4] sts %b exp %b", $time, ide_cmd, ide_exp);

		// check that pp sees it;

		pp_rw(0, 0, pp_cmd);
		pp_exp = 8'b0000_0101;
		if(pp_cmd !== pp_exp)
			$display("ERROR: %t: %M: pp[4] sts %b exp %b", $time, pp_cmd, pp_exp);
		if(IRQ !== 1'b0)
			$display("ERROR: %t: %M: pp[5] irq %b exp 0", $time, IRQ);

		// send ack host->bb;

		pp_cmd = 8'b0000_0010;
		pp_rw(1, 0, pp_cmd);
		pp_rw(0, 0, pp_cmd);
		pp_exp = 8'b0000_0111;
		if(pp_cmd !== pp_exp)
			$display("ERROR: %t: %M: pp[6] sts %b exp %b", $time, pp_cmd, pp_exp);

		// send ack host<-bb;

		ide_cmd = 8'b0000_0010;
		ide_rw(1, 0, 16'h4000, ide_cmd);
		ide_rw(0, 0, 16'h4000, ide_cmd);
		ide_exp = 16'b0000_1111;
		if(ide_cmd !== ide_exp)
			$display("ERROR: %t: %M: ide[7] sts %b exp %b", $time, ide_cmd, ide_exp);

		// clear pp intr;

		pp_cmd = 8'b0000_1100;
		pp_rw(1, 0, pp_cmd);
		pp_rw(0, 0, pp_cmd);
		pp_exp = 8'b0000_0011;
		if(pp_cmd !== pp_exp)
			$display("ERROR: %t: %M: pp[8] sts %b exp %b", $time, pp_cmd, pp_exp);
		if(IRQ !== 1'b1)
			$display("ERROR: %t: %M: pp[9] irq %b exp 1", $time, IRQ);

		// clear ide intr;

		ide_cmd = 8'b0000_1100;
		ide_rw(1, 0, 16'h4000, ide_cmd);
		ide_rw(0, 0, 16'h4000, ide_cmd);
		ide_exp = 16'b0000_0000;
		if(ide_cmd !== ide_exp)
			$display("ERROR: %t: %M: ide[10] sts %b exp %b", $time, ide_cmd, ide_exp);
		if(IOIRQ !== 1'b0)
			$display("ERROR: %t: %M: ide[11] irq %b exp 0", $time, IOIRQ);

		// done with simulation;

		$finish;
	end

endmodule