FDPE.v
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// $Header: /root/leakn64/depot/rf/hw/debug/xilinx/FDPE.v,v 1.1 2003/04/01 21:47:33 berndt Exp $
/*
FUNCTION : D-FLIP-FLOP with async preset and clock enable
*/
`timescale 100 ps / 10 ps
module FDPE (Q, C, CE, D, PRE);
parameter INIT = 1'b1;
output Q;
reg q_out;
input C, CE, D, PRE;
tri0 GSR = glbl.GSR;
buf B1 (Q, q_out);
always @(GSR or PRE)
if (GSR)
assign q_out = INIT;
else if (PRE)
assign q_out = 1;
else
deassign q_out;
always @(posedge C)
if (CE)
q_out <= D;
specify
(posedge PRE => (Q +: 1'b1)) = (1, 1);
if (!PRE && CE)
(posedge C => (Q +: D)) = (1, 1);
endspecify
endmodule