LDCP_1.v
774 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
// $Header: /root/leakn64/depot/rf/hw/debug/xilinx/LDCP_1.v,v 1.1 2003/04/01 21:47:34 berndt Exp $
/*
FUNCTION : D-LATCH with async clear, async preset
*/
`timescale 100 ps / 10 ps
module LDCP_1 (Q, CLR, D, G, PRE);
parameter INIT = 1'b0;
output Q;
reg q_out;
input CLR, D, G, PRE;
tri0 GSR = glbl.GSR;
buf B1 (Q, q_out);
always @(GSR or CLR or PRE or D or G)
if (GSR)
q_out <= INIT;
else if (CLR)
q_out <= 0;
else if (PRE)
q_out <= 1;
else if (!G)
q_out <= D;
specify
if (!CLR && !PRE && !G)
(D +=> Q) = (1, 1);
if (!CLR && !PRE)
(negedge G => (Q +: D)) = (1, 1);
if (!CLR)
(posedge PRE => (Q +: 1'b1)) = (1, 1);
(posedge CLR => (Q +: 1'b0)) = (1, 1);
endspecify
endmodule