// ifx.v v1 Frank Berndt
// ide-flash controller fpga;
// :set tabstop=4

// minimum of xc2s130 is required;
// xc2s50 is pin compatible and can be used as well;

// identify returns HD of 128GB size (lba28);
// with support for pio 0..2, dma 0..2, no udma;
// max dma rate at dma mode 2 is 16MB/sec;
//
// addressing, up to 1GB per flash;
//	lba[27:26] device address;
//	lba[25:23] 0 unused;
//	lba[22] read type 0=data+ecc 1=mfgid;
//	lba[21:0] page address;
//
// reads look only at lba[21:0];
//	read timing in hardware with automatic prefetch of next pages;
//	returned data block is 1k, 0..527 is data bytes, rest 0;
//	no ecc checking, correction or generation;
//
// writes upload microcode;
//	00000000 xxxxxxxx done and interrupt;
//	0111xxxx DDDDDDDD cmd phase
//	0110xxxx DDDDDDDD address phase
//	0101xxxx SSSSSSSS write data phase, followed by S bytes, padded to 16-bit words;
//	0100xxxx SSSSSSSS write data phase, followed by S bytes, padded to 16-bit words;
//	001xxxx0 zzzzzzzz bit 1 check for 0
//	001xxxx1 zzzzzzzz bit 1 check for 1
//	0100xxxx cccccccc config CLE/ALE active time
//	0101xxxx cccccccc config WE active time
//	0110xxxx cccccccc config RE active time
//	0111xxxx pcccxccc config write-protect, read sample time, end cycle time;
//	1ttttttt tttttttt wait for rdy 0->1 in 16 clocks, max 5.2ms @100
//
//	each command polls the MD signal and aborts with error if module is not present;
//	wait ready commands abort when timeout expired;

`timescale 1ns/1ns

module ifx (
	CLK,
	DRST, DD, DA, DCS, DIOR, DIOW, DIORDY, DMARQ, DMACK, DINTR, DIAG, DASP,
	FDB, FCE, FCLE, FALE, FRE, FWE, FWP, FRYBY, FMD,
	LED
);
	// global signals;

	input CLK;				// global clock;

	// ide bus interface;

	input DRST;				// ide bus reset;
	inout [15:0] DD;		// data bus;
	input [2:0] DA;			// addresses;
	input [1:0] DCS;		// chip selects;
	input DIOR;				// read strobe;
	input DIOW;				// write strobe;
	output DIORDY;			// io ready;
	output DMARQ;			// dma request;
	input DMACK;			// dma acknowledge;
	output DINTR;			// interrupt;
	inout DIAG;				// diagnostic signal;
	inout DASP;				// active/present signal;

	// flash interface;

	inout [7:0] FDB;		// data bus;
	output [2:0] FCE;		// chip selects;
	output FCLE;			// command latch enable;
	output FALE;			// address latch enable;
	output FRE;				// read pulse;
	output FWE;				// write pulse;
	output FWP;				// write protect;
	input FRYBY;			// ready/busy;
	input FMD;				// module detect;
	output [1:0] LED;		// one per led;

	// global clock;
	// external oscillator is 50Mhz;
	// double for internal operation;

	wire dll_locked;		// dll locked;
	wire in_clk;			// output of input buffer;
	wire clk2x;				// x2 dll clock output;
	wire gclk;				// global clock tree;

	IBUFG io_clk ( .I(CLK), .O(in_clk) );
	CLKDLL dll (
		.RST(1'b0), .LOCKED(dll_locked),
		.CLKIN(in_clk), .CLKFB(gclk),
		.CLK0(), .CLK90(), .CLK180(), .CLK270(), .CLK2X(clk2x)
	);
	BUFG g_clk ( .I(clk2x), .O(gclk) );

	// ide reset is chip reset;
	// use global buffer;

	wire in_drst;			// reset;
	wire grst;				// global reset;

	IBUF io_drst ( .I(DRST), .O(in_drst) );	// XXX pin and softreset;
	BUFG g_rst ( .I(~in_drst), .O(grst) );

	// ide data bus;
	// use io cells for fast t[su] and t[co];

	wire [15:0] in_dd;		// output of input buffer;
	reg [15:0] r_dd_in;		// input registers;
	wire [15:0] rdata;		// read data;
	reg [15:0] r_dd_out;	// output registers;
	wire roe;				// read output enable;
	reg [15:0] r_ddoe;		// output enable registers;

	IOBUF_F_12
		io_dd15 ( .IO(DD[15]), .I(r_dd_out[15]), .O(in_dd[15]), .T(r_ddoe[15]) ),
		io_dd14 ( .IO(DD[14]), .I(r_dd_out[14]), .O(in_dd[14]), .T(r_ddoe[14]) ),
		io_dd13 ( .IO(DD[13]), .I(r_dd_out[13]), .O(in_dd[13]), .T(r_ddoe[13]) ),
		io_dd12 ( .IO(DD[12]), .I(r_dd_out[12]), .O(in_dd[12]), .T(r_ddoe[12]) ),
		io_dd11 ( .IO(DD[11]), .I(r_dd_out[11]), .O(in_dd[11]), .T(r_ddoe[11]) ),
		io_dd10 ( .IO(DD[10]), .I(r_dd_out[10]), .O(in_dd[10]), .T(r_ddoe[10]) ),
		io_dd9 ( .IO(DD[9]), .I(r_dd_out[9]), .O(in_dd[9]), .T(r_ddoe[9]) ),
		io_dd8 ( .IO(DD[8]), .I(r_dd_out[8]), .O(in_dd[8]), .T(r_ddoe[8]) ),
		io_dd7 ( .IO(DD[7]), .I(r_dd_out[7]), .O(in_dd[7]), .T(r_ddoe[7]) ),
		io_dd6 ( .IO(DD[6]), .I(r_dd_out[6]), .O(in_dd[6]), .T(r_ddoe[6]) ),
		io_dd5 ( .IO(DD[5]), .I(r_dd_out[5]), .O(in_dd[5]), .T(r_ddoe[5]) ),
		io_dd4 ( .IO(DD[4]), .I(r_dd_out[4]), .O(in_dd[4]), .T(r_ddoe[4]) ),
		io_dd3 ( .IO(DD[3]), .I(r_dd_out[3]), .O(in_dd[3]), .T(r_ddoe[3]) ),
		io_dd2 ( .IO(DD[2]), .I(r_dd_out[2]), .O(in_dd[2]), .T(r_ddoe[2]) ),
		io_dd1 ( .IO(DD[1]), .I(r_dd_out[1]), .O(in_dd[1]), .T(r_ddoe[1]) ),
		io_dd0 ( .IO(DD[0]), .I(r_dd_out[0]), .O(in_dd[0]), .T(r_ddoe[0]) );

	always @(posedge gclk)
	begin
		r_dd_in <= in_dd;
		r_dd_out <= rdata;
		r_ddoe <= {16{~roe}};
	end

	// ide control inputs;
	// use io cells for fast t[su];

	wire [2:0] in_da;		// addresses;
	wire [1:0] in_dcs;		// chip selects;
	wire in_dior;			// read strobe;
	wire in_diow;			// write strobe;
	wire in_dmack;			// dma acknowledge;

	IBUF
		io_da0 ( .I(DA[0]), .O(in_da[0]) ),
		io_da1 ( .I(DA[1]), .O(in_da[1]) ),
		io_da2 ( .I(DA[2]), .O(in_da[2]) ),
		io_dcs0 ( .I(DCS[0]), .O(in_dcs[0]) ),
		io_dcs1 ( .I(DCS[1]), .O(in_dcs[1]) ),
		io_dior ( .I(DIOR), .O(in_dior) ),
		io_diow ( .I(DIOW), .O(in_diow) ),
		io_dmack ( .I(DMACK), .O(in_dmack) );

	reg [2:0] r_da;			// addresses;
	reg [1:0] r_dcs;		// chip selects;
	reg r_dior;				// read strobe;
	reg r_diow;				// write strobe;
	reg r_dmack;			// dma acknowledge;

	always @(posedge gclk)
	begin
		r_da <= in_da;
		r_dcs <= in_dcs;
		r_dior <= in_dior;
		r_diow <= in_diow;
		r_dmack <= in_dmack;
	end

	// ide control outputs;
	// use io cells for fast t[co];
	// IORDY is not used;

	wire ide_iordy;			// io ready;
	wire ide_dmarq;			// dma request;
	wire intr;				// interrupt output;
	reg r_iordy;			// io ready;
	reg r_intr;				// interrupt;

	assign ide_iordy = 1'b1;

	always @(posedge gclk)
	begin
		r_iordy <= ide_iordy;
		r_intr <= intr;
	end

	OBUFT_F_12 io_diordy ( .I(1'b0), .O(DIORDY), .T(r_iordy) );
	OBUF_F_12  io_dmarq ( .I(ide_dmarq), .O(DMARQ) );
	OBUF_F_12 io_dintr ( .I(r_intr), .O(DINTR) );

	// diag signals;
	// use io cells for fast t[su] and t[co];

	wire in_diag;			// output of input buffer;
	wire in_dasp;			// output of input buffer;
	reg r_diag_in;			// input registers;
	reg r_dasp_in;			// input registers;
	wire diag_out;			// DIAG output;
	wire dasp_out;			// DASP output;
	reg r_diag_out;			// output registers;
	reg r_dasp_out;			// output registers;
	wire diag_oe;			// DIAG output enable;
	wire dasp_oe;			// DASP output enable;

	IOBUF_F_12
		io_diag ( .IO(DIAG), .I(r_diag_out), .O(in_diag), .T(diag_oe) ),
		io_dasp ( .IO(DASP), .I(r_dasp_out), .O(in_dasp), .T(dasp_oe) );

	// XXX unused for usb ide bridge;

	assign diag_out = 1'b0;
	assign dasp_out = 1'b0;
	assign diag_oe = 1'b1;
	assign dasp_oe = 1'b1;

	always @(posedge gclk)
	begin
		r_diag_in <= in_diag;
		r_dasp_in <= in_dasp;
		r_diag_out <= diag_out;
		r_dasp_out <= dasp_out;
	end

	// global ide ctrl signals;

	wire dev_sel;				// device is selected;
	wire srst;					// soft reset;
	wire ie;					// interrupt enable;
	reg bsy;					// drive busy status;
	reg drq;					// data request status;
	wire busy;					// ide controller is busy;
	reg bdel;					// delayed busy;

	assign busy = bsy | drq;

	always @(posedge gclk)
	begin
		bdel <= busy;
	end

	// enable data output to ide bus;
	// only when device is selected;
	// pio: DIOR and one of DCS are asserted;
	// dma: DIOR and DMACK are asserted;

	assign roe = dev_sel & ~r_dior & ((r_dcs != 2'b11) | ~r_dmack);

	// synchronize input path;
	// all control signals and write data;

	reg [15:0] dd_in;		// delayed input data;
	reg [2:0] da;			// delayed address;
	reg [1:0] dcs;			// delayed chip selects;
	reg diow;				// delayed iow;
	reg dior;				// delayed ior;
	reg dmack;				// delayed dma ack;
	wire io_rd;				// io read pules, pio and dma;
	wire io_wr;				// io write pulse, pio and dma;
	wire io_rwx;			// io r/w pulse at ior/iow assertion;
	reg [15:0] din;			// latched input data;
	reg [2:0] adr;			// latched address;
	reg [1:0] cs;			// latched chip selects;
	reg ack;				// latched dma ack;
	reg io_wval;			// io write pulse;

	assign io_rd = r_dior & dior;
	assign io_wr = r_diow & diow;
	assign io_rwx = (~r_dior & ~dior) | (~r_diow & ~diow);

	always @(posedge gclk)
	begin
		dd_in <= r_dd_in;
		da <= r_da;
		dcs <= ~r_dcs;
		diow <= ~r_diow;
		dior <= ~r_dior;
		dmack <= ~r_dmack;
		if(io_wr) begin
			din <= dd_in;
			adr <= da;
			cs <= dcs;
			ack <= dmack;
		end
		if(grst)
			io_wval <= 1'b0;
		else
			io_wval <= io_wr;
	end

	// decode accesses to 16-bit port;
	// for all DMA read/write cycles and accesses to the data register;

	wire port16;			// access 16-bit data port;
	reg wr16;				// write to 16-bit port;
	reg rd16;				// read from 16-bit port;
	reg rw16;				// read or write access;

	assign port16 = ~r_dmack | (r_da == 3'd0);

	always @(posedge gclk)
	begin
		wr16 <= io_wr & port16;
		rd16 <= io_rd & port16;
		rw16 <= (io_wr | io_rd) & port16;
	end

	// decode register writes;
	// registers are written in both master and slave;
	// no action is taken when device is not selected,
	// except for the EXEC DEVICE DIAGNOSTICS command;
	// writes to CS[0]=0 are dropped if BSY=1;
	// writes to CS[1]=0 do not look at BSY;

	wire [7:0] reg_adec;		// register address decodes;
	wire [1:0] reg_write;		// write to registers, CS1 or CS0;
	reg [7:0] reg_wdata;		// register write data;
	reg [7:0] reg_we;			// register write enables;
	reg cdr_we;					// ctrl/diag register write enable;

	assign reg_adec[0] = (adr == 3'd0);
	assign reg_adec[1] = (adr == 3'd1);
	assign reg_adec[2] = (adr == 3'd2);
	assign reg_adec[3] = (adr == 3'd3);
	assign reg_adec[4] = (adr == 3'd4);
	assign reg_adec[5] = (adr == 3'd5);
	assign reg_adec[6] = (adr == 3'd6);
	assign reg_adec[7] = (adr == 3'd7);

	assign reg_write[0] = ~ack & io_wval & (cs == 2'b01) & ~bsy;
	assign reg_write[1] = ~ack & io_wval & (cs == 2'b10);

	always @(posedge gclk)
	begin
		reg_wdata <= din[7:0];
		reg_we[0] <= reg_write[0] & reg_adec[0];
		reg_we[1] <= reg_write[0] & reg_adec[1];
		reg_we[2] <= reg_write[0] & reg_adec[2];
		reg_we[3] <= reg_write[0] & reg_adec[3];
		reg_we[4] <= reg_write[0] & reg_adec[4];
		reg_we[5] <= reg_write[0] & reg_adec[5];
		reg_we[6] <= reg_write[0] & reg_adec[6];
		reg_we[7] <= reg_write[0] & reg_adec[7];
		cdr_we <= reg_write[1] & reg_adec[6];
	end

	// device registers;
	// writes to the data register go straight to the buffer;

	reg [7:0] feature;			// feature register;
	reg [7:0] sec_cnt;			// sector count;
	reg [7:0] sec_nbr;			// sector number;
	reg [7:0] cyl_low;			// cylinder low;
	reg [7:0] cyl_high;			// cylinder high;
	reg [7:0] sdh;				// drive/head;
	reg [7:0] cmd;				// command register;
	reg [2:1] dev_ctrl;			// device ctrl register;

	always @(posedge gclk)
	begin
		if(reg_we[1])
			feature <= reg_wdata;
		if(grst) begin
			sec_cnt <= 'd1;
			sec_nbr <= 'd1;
			cyl_low <= 'd0;
			cyl_high <= 'd0;
			sdh <= 'd0;
			dev_ctrl <= 2'b00;		// SRST=0, IEN=0 (enabled);
		end else begin
			if(reg_we[2])
				sec_cnt <= reg_wdata;
			if(reg_we[3])
				sec_nbr <= reg_wdata;
			if(reg_we[4])
				cyl_low <= reg_wdata;
			if(reg_we[5])
				cyl_high <= reg_wdata;
			if(reg_we[6])
				sdh <= reg_wdata;
			if(cdr_we)
				dev_ctrl <= reg_wdata[2:1];
		end
		if(reg_we[7])
			cmd <= reg_wdata;
	end

	assign dev_sel = ~sdh[4];
	assign srst = dev_ctrl[2];
	assign ie = ~dev_ctrl[1];

	// commit to ide command;
	// on write to cmd register when selected and BSY=0;
	// on write of EXEC DEVICE DIAGNOSTICS cmd;

	wire cmd_edd;				// cmd EXEC DEVICE DIAGNSTICS;
	reg [4:0] start;			// start ide command;

	assign cmd_edd = (cmd[7:0] == 8'b1001_0000);

	always @(posedge gclk)
	begin
		start[0] <= reg_we[7];
		start[1] <= start[0] & (dev_sel | cmd_edd);
		start[3:2] <= start[2:1];
	end

	// ide command decode;
	// cmd				code		F SC SN C SDH	operation
	// RECALIBRATE		0001_xxxx	- -  -  -  D	no-op
	// READ SECTOR		0010_00Lx	- v  v  v  v	read pio
	// READ LONG		0010_001x	- v  v  v  v	ERROR
	// READ DMA			1100_100x	- v  v  v  v	read dma
	// WRITE SECTOR		0011_00Lx	- v  v  v  v	write pio
	// WRITE LONG		0011_001x	- v  v  v  v	ERROR
	// WRITE DMA		1100_101x	- v  v  v  v	write dma
	// WRITE VERIFY		0011_1100	- v  v  v  v	ERROR
	// READ VERIFY		0100_000x	- v  v  v  v	ERROR
	// FORMAT TRACK		0101_0000	- -  -  v  v	ERROR
	// SEEK				0111_xxxx	- -  v  v  v	no-op
	// EXEC DIAG		1001_0000	- -  -  -  D	no-op
	// INIT PARAMS		1001_0001	- v  -  -  v	no-op
	// READ BUFFER		1110_0100	- -  -  -  D	ERROR
	// WRITE BUFFER		1110_1000	- -  -  -  D	ERROR
	// IDENTIFY			1110_1100	- -  -  -  D	read identify data
	// SET FEATURE		1110_1111	v -  -  -  D	no-op for unsupported
	// READ MULTIPLE	1100_0100	- v  v  v  v	read pio
	// WRITE MULTIPLE	1100_0101	- v  v  v  v	write pio
	// SET MULTIPLE		1100_0110	- v  -  -  D	set multiple size
	// POWER MODE		94,95,96,97,98,99			ERROR
	// POWER MODE		e0,e1,e2,e3,e5,e6			ERROR
	// SMART			b0							ERROR

	reg cmd_recalibrate;
	reg cmd_read_sec, cmd_read_dma, cmd_read_mult;
	reg cmd_write_sec, cmd_write_dma, cmd_write_mult;
	reg cmd_identify;
	reg cmd_seek;
	reg cmd_exec_diag;
	reg cmd_init_parm;
	reg cmd_set_feature;
	wire cmd_all;				// all supported cmds;
	reg cmd_nop;				// all no-op cmds;
	wire cmd_read;				// all read commands;
	wire cmd_write;				// all write commands;
	reg cmd_rd;					// all read commands;
	reg cmd_wr;					// all write commands;
	reg cmd_dma;				// all dma commands;
	reg cmd_illegal;			// illegal cmd, abort;
	wire abort_cmd;				// abort command;
	wire done_nop;				// done with no-op cmd;

	assign cmd_read = cmd_read_sec | cmd_read_dma | cmd_read_mult;
	assign cmd_write = cmd_write_sec | cmd_write_dma | cmd_write_mult;
	assign cmd_all = cmd_read | cmd_write
		| cmd_recalibrate | cmd_identify | cmd_seek
		| cmd_exec_diag | cmd_init_parm | cmd_set_feature;

	always @(posedge gclk)
	begin
		if(start[1]) begin
			cmd_recalibrate <= (cmd[7:4] == 4'b0001);
			cmd_read_sec <= (cmd[7:1] == 7'b0010_000);
			cmd_read_dma <= (cmd[7:1] == 7'b1100_100);
			cmd_read_mult <= (cmd[7:0] == 8'b1100_0100);
			cmd_write_sec <= (cmd[7:1] == 7'b0011_000);
			cmd_write_dma <= (cmd[7:1] == 7'b1100_101);
			cmd_write_mult <= (cmd[7:0] == 8'b1100_0101);
			cmd_identify <= (cmd[7:0] == 8'b1110_1100);
			cmd_seek <= (cmd[7:4] == 4'b0111);
			cmd_exec_diag <= cmd_edd;
			cmd_init_parm <= (cmd[7:0] == 8'b1001_0001);
			cmd_set_feature <= (cmd[7:0] == 8'b1110_1111);
		end
		cmd_rd <= cmd_read;
		cmd_wr <= cmd_write;
		cmd_dma <= cmd_read_dma | cmd_write_dma;
		cmd_nop <= cmd_recalibrate | cmd_seek
			| cmd_exec_diag | cmd_init_parm | cmd_set_feature;
		if(grst | start[1])
			cmd_illegal <= 1'b0;
		else if(start[2])
			cmd_illegal <= ~cmd_all;
		start[4] <= start[3] & ~(cmd_illegal | cmd_nop | cmd_identify);
	end

	assign abort_cmd = start[3] & cmd_illegal;
	assign done_nop = start[3] & cmd_nop;

	// sectors left;
	// counts in 512 byte sectors;
	// 0 in sec_cnt register means 256 sectors;

	reg [7:0] scnt;				// # of sectors left;
	reg scnt_dec;				// decrement scnt;
	reg scnt_rlast;				// last read sector;
	reg scnt_wlast;				// last write sector;

	always @(posedge gclk)
	begin
		if(start[2]) begin
			scnt <= sec_cnt;
			scnt_wlast <= 1'b0;
		end else if(scnt_dec) begin
			scnt <= scnt - 1;
			scnt_wlast <= scnt_rlast;
		end
		scnt_rlast <= cmd_identify | (scnt == 8'd1);
	end

	// special handling for illegal and nop commands;

	reg done_identify;			// donw with identify cmd;
	reg done;					// done with simple commands;

	always @(posedge gclk)
	begin
		done_identify <= cmd_identify & start[3];
		done <= abort_cmd | done_nop;
	end

	// LBA register;
	// must transfer from above registers when cmd is issued;
	// increments after each block;
	// points to block of first error;
	// this register is read back for LBA register reads;

	reg [27:0] lba;				// LBA register;
	reg lba_load;				// load new LBA;
	reg lba_inc;				// increment LBA;

	always @(posedge gclk)
	begin
		if(grst)
			lba_load <= 1'b1;
		else
			lba_load <= |reg_we[6:3];
		if(lba_load)
			lba <= { sdh[3:0], cyl_high, cyl_low, sec_nbr };
		else if(lba_inc)
			lba[21:0] <= lba[21:0] + 1;
	end

	// device ready flag, DRDY;
	// cleared on hard reset and soft reset;
	// set as soon as out of reset;

	reg drdy;					// drive ready status;

	always @(posedge gclk)
	begin
		if(grst)
			drdy <= 1'b0;
		else
			drdy <= ~srst;
	end

	// device BSY/DRQ handling;
	// toggle between the two as long as more data is pending;
	// the OR of both is the ctrl busy flag;
	//
	// reads:
	//            _                _
	// set_bsy __/ \______________X_X___
	//              ________         ___
	// bsy     ____/        \_______X___
	//                     _
	// clr_bsy ___________/ \___________
	//                       _______   
	// drq     _____________/       \___
	//
	// writes:
	//                       _______   
	// bsy     _____________/       \___
	//            _                _
	// set_drq __/ \______________X_X___
	//              ________         ___
	// drq     ____/        \_______X___
	//                     _
	// clr_drq ___________/ \___________

	reg bsy_done;				// io side done with sector buffer;
	reg drq_done;				// ide side done with sector buffer;
	reg drq_busy;				// drq still busy on ide bus;
	reg drq_rel;				// drq done with ide bus;

	// device busy flag, BSY;
	// set while device:
	//	- fills the sector/block buffer from medium;
	//	- writes the sector/block buffer to medium;
	//	- on dma command issue;
	// cleared:
	//	- when sector/block buffer is available;
	//	- on command completion;

	wire bsy_set_rd;			// set bsy for read;
	wire bsy_set_wr;			// set bsy for write;
	wire bsy_set;				// set bsy;
	reg bsy_del;				// min of one busy delay is needed for scnt_wlast;
	reg bsy_req;				// request flash op;
	wire bsy_ack;				// ack completion of flash op;
	wire bsy_err;				// flash errors;

	assign bsy_set_rd = cmd_rd & (start[4] | (drq_done & ~scnt_rlast));
	assign bsy_set_wr = cmd_wr & drq_done;
	assign bsy_set = bsy_set_rd | bsy_set_wr;

	always @(posedge gclk)
	begin
		bsy <= ~grst & ~bsy_done & (bsy | bsy_set);
		bsy_del <= bsy_set;
		bsy_req <= bsy & (drq_busy? drq_rel : bsy_del);
		bsy_done <= bsy_ack;
		lba_inc <= bsy_done;
	end

	// device data request status, DRQ;
	// set:
	//	- when sector/block buffer is available for fill/read;
	//	- IDENTIFY data are available;
	// cleared:
	//	- when host emptied/filled the sector/block buffer;

	wire drq_set_rd;			// set drq for read;
	wire drq_set_wr;			// set drq for write;
	wire drq_set;				// set drq;

	assign drq_set_rd = done_identify | (cmd_rd & bsy_done);
	assign drq_set_wr = cmd_wr & (start[4] | (bsy_done & ~scnt_wlast));
	assign drq_set = drq_set_rd | drq_set_wr;

	always @(posedge gclk)
	begin
		drq <= ~grst & ~drq_done & (drq | drq_set);
		drq_busy <= ~grst & ~drq_rel & (drq_busy | drq);
	end

	assign ide_dmarq = drq & cmd_dma;

	// device error status; ERR;

	reg err;					// cmd terminated with error;
	wire err_clr;				// clear error flag;
	wire err_set;				// set error flag;

	assign err_clr = grst | start[1];
	assign err_set = abort_cmd | bsy_err;

	always @(posedge gclk)
	begin
		if(err_clr)
			err <= 1'b0;
		else if(err_set)
			err <= 1'b1;
	end

	// device status register;

	wire [7:0] status;			// status register;

	assign status = { bsy, drdy, 2'b01, drq, 2'b00, err };

	// interrupt handling;
	// set:
	//	- on cmd completion without error;
	//	- on cmd completion with error/abort;
	//	- when ready to send data for pio data-in cmds;
	//	- when ready to acept another block for pio data-out cmds;
	//	- when device 0 completes the EXEC DEVICE DIAGNOSTICS cmd;
	// cleared:
	//	- on DRST=0;
	//	- on SRST=1;
	//	- when device is selected, BSY=0 and STATUS reg is read;
	//	- when device is selected, BSY=0 DRQ=0 and CMD reg is written;
	// the host changing DEV_SEL shall not change the intr pending state;
	// pending intr are output on INTRQ as soon as IEN is enabled;

	reg intr_clr_rsts;			// clear intr on read of status reg;
	wire intr_clr_ncmd;			// clear intr on new command;
	reg intr_clr;				// clear ide intr;
	reg intr_set_pio;			// set intr for pio data block;
	reg intr_set_dma;			// set intr for dma completion;
	reg intr_set;				// set ide intr;
	reg intr_pend;				// interrupt is pending;

	assign intr_clr_ncmd = start[1]; //XXX DRQ??

	always @(posedge gclk)
	begin
		intr_clr_rsts <= dev_sel & dior & ~dmack & (dcs == 2'b01) & (da == 3'd7);
		intr_clr <= srst | intr_clr_rsts | intr_clr_ncmd;
		intr_set_pio <= ~cmd_dma & bsy_done;
		intr_set_dma <= cmd_dma & bdel & ~busy;
		intr_set <= done | done_identify | intr_set_pio | intr_set_dma;
		intr_pend <= ~grst & ~intr_clr & (intr_pend | intr_set);
	end

	assign intr = intr_pend & ie;

	// error register;
	// return abort in case of error, no retries;

	wire [7:0] error;			// error register;

	assign error[7] = 1'b0;		// no interface crc errors, no udma;
	assign error[6] = 1'b0;		// no data crc/ecc error;
	assign error[5] = 1'b0;		// unused;
	assign error[4] = 1'b0;		// unused;
	assign error[3] = 1'b0;		// no id not found errors;
	assign error[2] = err;		// cmd aborted;
	assign error[1] = 1'b0;		// no track 0 errors;
	assign error[0] = 1'b0;		// no address mark not found errors;

	// register read data mux;
	// register reads returns the STATUS reg when BSY=1;
	// dma reads and data reg reads return 16 bits;

	reg [15:0] data_out;		// data out register, pio and dma;
	reg [2:0] raddr;			// read address;
	reg sel_sts;				// read from status reg if busy;
	reg [7:0] rudata;			// upper read data;
	reg [7:0] rldata;			// lower read data;

	always @(posedge gclk)
	begin
		if(r_dmack == 1'b0)
			raddr <= 3'd0;
		else
			raddr <= r_da;
		sel_sts <= (bsy & ~port16) | ~r_dcs[1];
		rudata <= {8{port16}} & data_out[15:8];
		case(raddr)
			3'd0: rldata <= data_out[7:0];
			3'd1: rldata <= error;
			3'd2: rldata <= sec_cnt;
			3'd3: rldata <= lba[7:0];			// sec_nbr;
			3'd4: rldata <= lba[15:8];			// cyl_low;
			3'd5: rldata <= lba[23:16];			// cyl_high;
			3'd6: rldata <= { sdh[7:4], lba[27:24] };
			3'd7: rldata <= status;
		endcase
	end

	assign rdata[15:8] = rudata;
	assign rdata[7:0] = sel_sts? status : rldata;


	// sram buffer;
	// two 1kbyte dual-port buffers;
	// one in use, the other for prefetch;
	// port A is ide side, port B is flash side;
	// organized as 1kx16, using 4 block rams;

	wire ib_ena;				// ide port enable;
	wire [9:0] ib_addr;			// ide read/write address;
	wire [15:0] ib_wdata;		// ide write data;
	wire ib_we;					// ide write enable;
	wire [15:0] ib_xdata;		// ide read data;
	wire ib_rz;					// ide read 0;

	wire fb_ena;				// flash port enable;
	wire [9:0] fb_addr;			// flash read/write address;
	wire [7:0] fb_wdata;		// flash write data;
	reg [1:0] fb_we;			// flash byte write enables;
	wire [15:0] fb_xdata;		// flash read data;
	wire fb_rz;					// flash read 0;

	assign ib_ena = drq_busy;
	assign ib_wdata = din;
	assign ib_we = wr16;
	assign ib_rz = cmd_identify;

	assign fb_rz = 1'b0;

	RAMB4_S4_S4 b0 (
		.CLKA(gclk), .ENA(ib_ena), .RSTA(ib_rz),
		.ADDRA(ib_addr), .DIA(ib_wdata[3:0]), .WEA(ib_we), .DOA(ib_xdata[3:0]),
		.CLKB(gclk), .ENB(fb_ena), .RSTB(fb_rz),
		.ADDRB(fb_addr), .DIB(fb_wdata[3:0]), .WEB(fb_we[0]), .DOB(fb_xdata[3:0])
	);
	RAMB4_S4_S4 b1 (
		.CLKA(gclk), .ENA(ib_ena), .RSTA(ib_rz),
		.ADDRA(ib_addr), .DIA(ib_wdata[7:4]), .WEA(ib_we), .DOA(ib_xdata[7:4]),
		.CLKB(gclk), .ENB(fb_ena), .RSTB(fb_rz),
		.ADDRB(fb_addr), .DIB(fb_wdata[7:4]), .WEB(fb_we[0]), .DOB(fb_xdata[7:4])
	);
	RAMB4_S4_S4 b2 (
		.CLKA(gclk), .ENA(ib_ena), .RSTA(ib_rz),
		.ADDRA(ib_addr), .DIA(ib_wdata[11:8]), .WEA(ib_we), .DOA(ib_xdata[11:8]),
		.CLKB(gclk), .ENB(fb_ena), .RSTB(fb_rz),
		.ADDRB(fb_addr), .DIB(fb_wdata[3:0]), .WEB(fb_we[1]), .DOB(fb_xdata[11:8])
	);
	RAMB4_S4_S4 b3 (
		.CLKA(gclk), .ENA(ib_ena), .RSTA(ib_rz),
		.ADDRA(ib_addr), .DIA(ib_wdata[15:12]), .WEA(ib_we), .DOA(ib_xdata[15:12]),
		.CLKB(gclk), .ENB(fb_ena), .RSTB(fb_rz),
		.ADDRB(fb_addr), .DIB(fb_wdata[7:4]), .WEB(fb_we[1]), .DOB(fb_xdata[15:12])
	);

	// identify rom;
	// one 512 byte buffer, 256x16;
	// only connected to ide side;

	wire id_ena;				// enable ide rom;
	wire [15:0] id_xdata;		// id read data;
	wire id_rz;					// id read 0;

	assign id_ena = 1'b1;
	assign id_rz = ~cmd_identify;

	RAMB4_S16 idrom (
		.CLK(gclk), .EN(id_ena), .RST(id_rz),
		.ADDR(ib_addr[7:0]), .DI(16'd0), .WE(1'b0), .DO(id_xdata)
	);

`include "idrom.init"

	// buffer ide and flash read data flops;
	// ib_xdata and id_xdata can be ORed because of rz use;

	always @(posedge gclk)
	begin
		data_out <= ib_xdata | id_xdata;
	end

	// ide side buffer address;
	// adresses 16-bit words in buffer;
	// set to 0 at start of new command;
	// increments after each word access;

	reg i_addr_zero;			// zero ide buffer address;
	wire i_addr_inc;			// increment i_addr;
	reg [9:0] i_addr;			// buffer address;
	reg i_addr_last;			// last word in sector;

	assign i_addr_inc = rw16;

	always @(posedge gclk)
	begin
		i_addr_zero <= grst | start[1];
		if(i_addr_zero)
			i_addr <= 10'd0;
		else if(i_addr_inc)
			i_addr <= i_addr + 1;
		i_addr_last <= (i_addr[7:0] == 8'hff);
		drq_done <= i_addr_last & io_rwx & port16;
		drq_rel <= i_addr_last & i_addr_inc;
		scnt_dec <= drq_done;
	end

	assign ib_addr = i_addr;

	// flash interface;

	// flash data bus;
	// use io cells for fast t[su] and t[co];

	wire [7:0] in_fdb;		// output of input buffer;
	reg [7:0] f_in;			// input registers;
	reg [7:0] f_out;		// output data;
	reg [7:0] r_fout;		// output registers;
	wire f_noe;				// output enable;
	reg [7:0] r_foe;		// output enable registers;
	reg f_ien;				// capture input data;
	reg [7:0] f_din;		// data in capture register;

	IOBUF_F_12
		io_fdb7 ( .IO(FDB[7]), .I(r_fout[7]), .O(in_fdb[7]), .T(r_foe[7]) ),
		io_fdb6 ( .IO(FDB[6]), .I(r_fout[6]), .O(in_fdb[6]), .T(r_foe[6]) ),
		io_fdb5 ( .IO(FDB[5]), .I(r_fout[5]), .O(in_fdb[5]), .T(r_foe[5]) ),
		io_fdb4 ( .IO(FDB[4]), .I(r_fout[4]), .O(in_fdb[4]), .T(r_foe[4]) ),
		io_fdb3 ( .IO(FDB[3]), .I(r_fout[3]), .O(in_fdb[3]), .T(r_foe[3]) ),
		io_fdb2 ( .IO(FDB[2]), .I(r_fout[2]), .O(in_fdb[2]), .T(r_foe[2]) ),
		io_fdb1 ( .IO(FDB[1]), .I(r_fout[1]), .O(in_fdb[1]), .T(r_foe[1]) ),
		io_fdb0 ( .IO(FDB[0]), .I(r_fout[0]), .O(in_fdb[0]), .T(r_foe[0]) );

	always @(posedge gclk)
	begin
		f_in <= in_fdb;
		r_fout <= f_out;
		r_foe <= {8{f_noe}};
		if(f_ien)
			f_din <= f_in;
	end

	assign fb_wdata = f_din;

	// flash control outputs;
	// use io cells for fast t[co];

	wire [2:0] f_ce;		// chip enables;
	wire f_cle;				// cmd latch enable;
	wire f_ale;				// address latch enable;
	wire f_we;				// write enable;
	wire f_re;				// read enable;
	reg f_wp;				// flash write protect;
	reg [1:0] led;			// led status;
	reg [2:0] r_ce;			// chip enables;
	reg r_cle;				// cle output flop;
	reg r_ale;				// ale output flop;
	reg r_we;				// we output flop;
	reg r_re;				// re output flop;
	reg r_wp;				// wp output flop;
	reg [1:0] r_led;		// led output flops;

	always @(posedge gclk)
	begin
		r_ce <= ~f_ce;
		r_cle <= f_cle;
		r_ale <= f_ale;
		r_we <= ~f_we;
		r_re <= ~f_re;
		r_wp <= f_wp;
		r_led <= led;
	end

	OBUF_F_12
		io_fce2 ( .I(r_ce[2]), .O(FCE[2]) ),
		io_fce1 ( .I(r_ce[1]), .O(FCE[1]) ),
		io_fce0 ( .I(r_ce[0]), .O(FCE[0]) ),
		io_fcle ( .I(r_cle), .O(FCLE) ),
		io_fale ( .I(r_ale), .O(FALE) ),
		io_fwe ( .I(r_we), .O(FWE) ),
		io_fre ( .I(r_re), .O(FRE) ),
		io_fwp ( .I(r_wp), .O(FWP) );

	OBUF_F_24
		ioled1 ( .I(r_led[1]), .O(LED[1]) ),
		ioled0 ( .I(r_led[0]), .O(LED[0]) );

	// flash control inputs;
	// use io cell for fast t[su];
	// pass through another flop for synchronization;

	wire in_ryby;			// output of input buffer;
	wire in_md;				// output of input buffer;

	IBUF
		io_fryby ( .I(FRYBY), .O(in_ryby) ),
		io_fmd ( .I(FMD), .O(in_md) );

	reg r_ryby;				// 0=busy, 1=ready;
	reg r_md;				// module detect, 0=present;
	reg [2:0] ryby;			// synchronizer and edge-detection flops;
	reg md;					// synchronizer flop;

	always @(posedge gclk)
	begin
		r_ryby <= in_ryby;
		r_md <= in_md;
		ryby[1:0] <= { ryby[0], r_ryby };
		ryby[2] <= (ryby[1:0] == 2'b01);
		md <= r_md;
	end

	// flash controller state machine;

	// flash page read address;
	// address for writes comes out of micro code;
	// loaded from ide registers on first request;
	// read address increments at end of current page;
	// prefetch of next page is done automatically;

	reg [20:0] paddr;			// page address;
	reg paddr_ld;				// load new page address;
	reg paddr_sh;				// shift page address;

	always @(posedge gclk)
	begin
		if(paddr_ld)
			paddr <= lba[21:1];
		else if(paddr_sh)
			paddr <= { 8'd0, paddr[20:8] };
	end

	// read command rom;
	// contains mcode sequence for read commands;
	// 0: read page;
	//	 0 cmd 0x00;
	//	 1 addr 0x00;
	//	 2 addr addr[16:9];
	//	 3 addr addr[24:17];
	//	 4 addr addr[32:25];
	//	 5 wait rdy, 25us;
	//	 6 read block, 528 bytes;
	//	 7 done;
	// 8: read mfg id;
	//	 8 cmd 0x90;
	//	 9 addr 0x00;
	//	10 read block, 512 bytes;
	//	11 done;

	reg [3:0] xrom_addr;		// read address;
	wire [15:0] xrom_xdata;		// micro-code;

	RAM16X1S
		xrom15 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[15]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom14 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[14]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom13 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[13]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom12 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[12]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom11 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[11]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom10 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[10]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom09 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[9]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom08 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[8]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom07 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[7]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom06 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[6]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom05 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[5]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom04 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[4]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom03 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[3]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom02 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[2]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom01 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[1]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) ),
		xrom00 ( .WCLK(gclk), .WE(1'b0), .D(1'b0), .O(xrom_xdata[0]),
			.A0(xrom_addr[0]), .A1(xrom_addr[1]), .A2(xrom_addr[2]), .A3(xrom_addr[3]) );

`ifdef	SIM
	defparam xrom15.INIT = 16'b0000_0000_0010_0000;
	defparam xrom14.INIT = 16'b0000_0111_0101_1111;
	defparam xrom13.INIT = 16'b0000_0011_0001_1111;
	defparam xrom12.INIT = 16'b0000_0001_0000_0001;
	defparam xrom11.INIT = 16'b0000_0000_0000_0000;
	defparam xrom10.INIT = 16'b0000_0000_0000_0000;
	defparam xrom09.INIT = 16'b0000_0000_0100_0000;
	defparam xrom08.INIT = 16'b0000_0000_0001_1100;
	defparam xrom07.INIT = 16'b0000_0001_0010_0000;
	defparam xrom06.INIT = 16'b0000_0000_0000_0000;
	defparam xrom05.INIT = 16'b0000_0000_0010_0000;
	defparam xrom04.INIT = 16'b0000_0001_0000_0000;
	defparam xrom03.INIT = 16'b0000_0000_0100_0000;
	defparam xrom02.INIT = 16'b0000_0100_0100_0000;
	defparam xrom01.INIT = 16'b0000_0100_0100_0000;
	defparam xrom00.INIT = 16'b0000_0100_0100_0000;
`endif	// SIM

	// micro code engine;
	// reads are started when lba[0] is 0, aligned to 1k;
	// unaligned reads will return old data from sector buffer;
	// writes are processed per 512-byte blocks;
	// DWR and DRD cannot cross 512-byte boundaries;

	reg mstart;				// start micro-code execution;
	reg mdone;				// done with all micro-code;
	reg mbusy;				// busy with micro-code;
	reg mwrite;				// write command;

	assign bsy_ack = (cmd_rd & lba[0] & bsy_req) | mdone;

	always @(posedge gclk)
	begin
		mstart <= ~(cmd_rd & lba[0]) & bsy_req;
		mbusy <= ~grst & ~mdone & (mbusy | mstart);
		if(mstart)
			mwrite <= cmd_wr;
	end

	assign fb_ena = mbusy;

	// read rom microcode address;
	// set to READ PAGE (0) or READ MFG (8) index;

	reg xrom_inc;			// increment xrom_addr;

	always @(posedge gclk)
	begin
		if(mstart)
			xrom_addr <= lba[22]? 8 : 0;
		else if(xrom_inc)
			xrom_addr <= xrom_addr + 1;
	end

	// flash buffer address;

	wire [1:0] mbuf;			// flash side buffer index;
	reg [9:0] maddr;		// buffer word address;
	reg madd0;				// buffer byte address;
	wire maddr_zero;		// zero buf address;
	wire maddr_minc;		// increment maddr for micro-codes;
	wire maddr_bclr;		// clear byte offset;
	wire maddr_binc;		// increment maddr per byte;
	wire f_winc;			// increment maddr for write data;
	reg maddr_inc;			// increment maddr;
	wire mdrd_en;			// enable writing read data to buffer;

	assign maddr_zero = mstart;
	assign mbuf = cmd_wr? { i_addr[9:8] - 1 } : { i_addr[9], 1'b0 };

	always @(posedge gclk)
	begin
		if(maddr_zero)
			maddr <= { mbuf, 8'd0 };
		else if(maddr_inc)
			maddr <= maddr + 1;
		if(maddr_bclr)
			madd0 <= 1'b0;
		else if(maddr_binc)
			madd0 <= ~madd0;
		maddr_inc <= maddr_minc | (madd0 & maddr_binc);
		fb_we[0] <= f_ien & mdrd_en & ~madd0;
		fb_we[1] <= f_ien & mdrd_en & madd0;
	end

	assign maddr_binc = f_ien | f_winc;
	assign fb_addr = maddr;

	// latch micro-code from xrom or buffer;
	// stall until micro-code has been executed;
	// decode micro-code;
	//
	//	1ttttttt tttttttt	WRDY	wait for rdy 0->1, in 16 clocks, max 5.2ms @100
	//	0111xxxx DDDDDDDD	CMD		cmd cycle;
	//	0110xxxx DDDDDDDD	ADDR	address cycle;
	//	0101xxNN NNNNNNNN	DWR		data write cycle, N bytes;
	//	0100xxNN NNNNNNNN	DRD		data read cycle, N bytes;
	//	0011xxNN NNNNNNNN	SCHK	status check;
	//	0010xxxx rRgGxxSC	CTRL	C=1 clr, S=1 set semaphore, rg = led control
	//	0001xxRR cccccccc	CONF	write to config reg rr;
	//	0000xxxx xxxxxxxx	DONE	done;

	reg [3:0] mreq;				// micro pipe;
	reg [15:0] mcode;			// micro-code;
	reg [7:0] mlbyte;			// low byte of mcode;
	reg mstall;					// stall execution;
	reg merr;					// error during execution;
	reg mop_wrdy;				// wait-rdy;
	reg mop_fio;				// flash io;
	reg mop_csel;				// select cmd/addr;
	reg mop_asel;				// select read address;
	reg mop_dsel;				// select read/write data;
	reg mop_wsel;				// select write data;
	reg mop_schk;				// status check;
	reg mop_ctrl;				// write to ctrl register;
	reg mop_conf;				// write to config registers;
	reg mop_done;				// done instruction;
	wire wrdy_cont;				// continue after wrdy event;
	reg wrdy_to;				// wrdy timeout;
	reg flx_cont;				// continue after flx done;
	reg flx_err;				// flash io error;
	reg schk_cont;				// continue after status check;
	reg schk_err;				// status check failed;
	reg mcont;					// unstall and continue;

	always @(posedge gclk)
	begin
		mreq <= { mreq[2:0], mstart | mcont };
		if(mreq[1])
			mcode <= mwrite? fb_xdata : xrom_xdata;
		mlbyte <= mcode[7:0];
		mstall <= mbusy & ~mcont & (mstall | mreq[2]);
		if(mbusy == 1'b0) begin
			mop_wrdy <= 1'b0;
			mop_fio <= 1'b0;
			mop_csel <= 1'b0;
			mop_asel <= 1'b0;
			mop_dsel <= 1'b0;
			mop_wsel <= 1'b0;
		end else if(mreq[2]) begin
			mop_wrdy <= mcode[15];
			mop_fio <= (mcode[15:14] == 2'b01);
			mop_csel <= (mcode[15:13] == 3'b011);
			mop_asel <= (mcode[15:12] == 4'd6) & mcode[8];
			mop_dsel <= (mcode[15:13] == 3'b010);
			mop_wsel <= (mcode[15:12] == 4'd5);
		end
		mop_schk <= mreq[3] & (mcode[15:12] == 4'd3);
		mop_ctrl <= mreq[2] & (mcode[15:12] == 4'd2);
		mop_conf <= mreq[2] & (mcode[15:12] == 4'd1);
		mop_done <= mreq[2] & (mcode[15:12] == 4'd0);
		if(mbusy == 1'b0)
			mcont <= 1'b0;
		else
			mcont <= mop_ctrl | mop_conf | flx_cont | wrdy_cont | schk_cont;
		xrom_inc <= mcont;
		merr <= wrdy_to | flx_err | schk_err;
		mdone <= mop_done | merr;
	end

	assign maddr_minc = mwrite & mreq[0];
	assign maddr_bclr = ~mop_dsel;
	assign mdrd_en = ~mcode[11];
	assign bsy_err = merr;

	// micro-code repeat/size counter;
	// contains size - 1;
	// WRDY: loaded with timeout;
	// DWR/DRD: loaded with byte count;
	// else: loaded with 0;

	wire mcnt_low;				// use lower 10 bits of mcnt;
	wire [15:0] mcnt_val;		// mcnt load value;
	reg [15:0] mcnt;			// delay/byte counter;
	wire mcnt_load;				// load mcnt;
	wire mcnt_dec;				// decrement mcnt;

	assign mcnt_low = mcode[15] | (mcode[15:13] == 3'b010);
	assign mcnt_val[15] = 1'b0;
	assign mcnt_val[14:10] = {5{mcode[15]}} & mcode[14:10];
	assign mcnt_val[9:0] = {10{mcnt_low}} & mcode[9:0];
	assign mcnt_load = mreq[2];

	always @(posedge gclk)
	begin
		if(mcnt_load)
			mcnt <= mcnt_val;
		else if(mcnt_dec)
			mcnt <= mcnt - 1;
	end

	// wait-rdy divider;
	// divide gclk by 16;

	reg [3:0] wrdy_div;			// wrdy divider;
	reg wrdy_tick;				// wrdy :16 tick;

	always @(posedge gclk)
	begin
		if(mop_wrdy == 1'b0)
			wrdy_div <= {4{1'b1}};
		else
			wrdy_div <= wrdy_div - 1;
		wrdy_tick <= (wrdy_div == 4'd0);
		wrdy_to <= mop_wrdy & mcnt[15] & wrdy_tick;
	end

	assign wrdy_cont = mop_wrdy & ryby[2];

	// status check;
	// check for 0s or 1s;
	// lower mcode is bit mask;

	reg schk_xor;				// check 0 or 1 bits;
	reg schk_fail;				// bit check failed;

	always @(posedge gclk)
	begin
		schk_xor <= mcode[8];
		schk_fail <= |((f_din ^ {8{schk_xor}}) & mlbyte);
		schk_cont <= mop_schk & ~schk_fail;
		schk_err <= mop_schk & schk_fail;
	end

	// semaphore/led/wp control;
	// two-bit ops to clear and set;
	// clear had higher priority than set;
	// clear sema and wp when module is not present;

	reg sema;					// semaphore;
	wire [3:0] c_clr;			// clear ops;
	wire [3:0] c_set;			// set ops;

	assign c_clr[0] = (mop_ctrl & mlbyte[0]) | md;
	assign c_set[0] = mop_ctrl & mlbyte[1];
	assign c_clr[1] = (mop_ctrl & mlbyte[2]) | md;
	assign c_set[1] = mop_ctrl & mlbyte[3];
	assign c_clr[2] = mop_ctrl & mlbyte[4];
	assign c_set[2] = mop_ctrl & mlbyte[5];
	assign c_clr[3] = mop_ctrl & mlbyte[6];
	assign c_set[3] = mop_ctrl & mlbyte[7];

	always @(posedge gclk)
	begin
		if(grst) begin
			sema <= 1'b0;
			f_wp <= 1'b0;
			led <= 2'b00;
		end else begin
			sema <= ~c_clr[0] & (sema | c_set[0]);
			f_wp <= ~c_clr[1] & (f_wp | c_set[1]);
			led[0] <= ~c_clr[2] & (led[0] | c_set[2]);
			led[1] <= ~c_clr[3] & (led[1] | c_set[3]);
		end
	end

	// flash interface control;
	// issue requests until mcnt has reached 0;

	reg flx_val;				// start a new flash r/w cycle;
	wire flx_fin;
	reg flx_done;				// done with io cycle;

	assign flx_fin = mop_fio & mcnt[15] & flx_done;

	always @(posedge gclk)
	begin
		flx_val <= mop_fio & (mreq[3] | (~mcnt[15] & flx_done));
		flx_cont <= flx_fin & sema;
		flx_err <= flx_fin & ~sema;
	end

	assign mcnt_dec = flx_val | wrdy_tick;

	// read page address control;
	// load paddr upon mstart;
	// shift right after every ADDR instruction;

	always @(posedge gclk)
	begin
		paddr_ld <= mstart;
		paddr_sh <= mop_asel & flx_cont;
	end

	// flash write data mux;
	// select cmd (1 byte), READ, READ_STATUS or READ_MFG,
	// select page read address (3 bytes) or
	// select byte from buffer (2 bytes);
	// the flash READ cmd is 0x00;
	// page reads always start at begin of page, addr[8:0]=0x00;

	wire [7:0] f_cmd;			// cmd/addr byte;
	wire [7:0] f_dwr;			// write data from buffer;
	wire [7:0] f_dout;			// final output data;

	assign f_cmd = mop_asel? paddr[7:0] : mcode[7:0];
	assign f_dwr = madd0? fb_xdata[15:8] : fb_xdata[7:0];
	assign f_dout = ({8{mop_csel}} & f_cmd) | ({8{mop_wsel}} & f_dwr);

	always @(posedge gclk)
	begin
		f_out <= f_dout;
	end

	// flash timing configuration;
	// written by write data micro code;
	// defaults to slowest timing on reset;
	// reset timing on set of semaphore;

	reg f_conf_rst;			// reset flash configuration;
	wire [3:0] f_conf_wr;		// write to conf regs;
	reg [2:0] f_conf_eoc;		// end of cycle time;
	reg [2:0] f_conf_rs;		// read sample time;
	reg [7:0] f_conf_re;		// read enable active time;
	reg [7:0] f_conf_we;		// read enable active time;
	reg [7:0] f_conf_ac;		// ale/cle active times;

	assign f_conf_wr[0] = mop_conf & (mcode[9:8] == 2'd0);
	assign f_conf_wr[1] = mop_conf & (mcode[9:8] == 2'd1);
	assign f_conf_wr[2] = mop_conf & (mcode[9:8] == 2'd2);
	assign f_conf_wr[3] = mop_conf & (mcode[9:8] == 2'd3);

	always @(posedge gclk)
	begin
		f_conf_rst <= grst | c_set[0];
		if(f_conf_rst) begin
			f_conf_eoc <= 3'd7;			// 8 clock cycle;
			f_conf_rs <= 3'd5;			// read sample time;
			f_conf_re <= 8'b00111110;	// 5 clock read pulse;
			f_conf_we <= 8'b00111110;	// 5 clock write pulse;
			f_conf_ac <= 8'b11111111;	// 8 clock cycle;
		end else begin
			if(f_conf_wr[3]) begin
				f_conf_eoc <= mlbyte[6:4];
				f_conf_rs <= mlbyte[2:0];
			end
			if(f_conf_wr[2])
				f_conf_re <= mlbyte;
			if(f_conf_wr[1])
				f_conf_we <= mlbyte;
			if(f_conf_wr[0])
				f_conf_ac <= mlbyte;
		end
	end

	// decode flash ops;

	wire flc_cle;				// cmd cycle;
	wire flc_ale;				// address cycle;
	wire flc_we;				// write cycle;
	wire flc_re;				// read cycle;

	assign flc_cle = (mcode[13:12] == 2'b11);
	assign flc_ale = (mcode[13:12] == 2'b10);
	assign flc_we = |mcode[13:12];
	assign flc_re = (mcode[13:12] == 2'b00);

	// flash read/write cycle state machine;
	// flx_type determines cycle type;

	reg flx_cle;				// command latch cycle;
	reg flx_ale;				// address latch cycle;
	reg flx_we;					// write cycle;
	reg flx_re;					// read cycle;
	reg flx_busy;				// busy with flash cycle;
	reg [2:0] flx_cnt;			// flash cycle count;
	reg [7:0] flx_pipe;			// flash cycle pipe;
	wire flx_eoc;				// end of cycle;

	assign flx_eoc = (flx_cnt == f_conf_eoc);

	always @(posedge gclk)
	begin
		if(flx_val) begin
			flx_cle <= flc_cle;
			flx_ale <= flc_ale;
			flx_we <= flc_we;
			flx_re <= flc_re;
		end
		if(grst) begin
			flx_busy <= 1'b0;
			flx_pipe <= 8'd0;
		end else begin
			flx_busy <= ~flx_done & (flx_busy | flx_val);
			flx_pipe <= { flx_pipe[6:0], flx_val };
		end
		if(flx_busy == 1'b0)
			flx_cnt <= 3'd0;
		else
			flx_cnt <= flx_cnt + 1;
		flx_done <= flx_eoc;
		f_ien <= flx_re & (flx_cnt == f_conf_rs);
	end

	assign f_winc = mop_wsel & flx_eoc;

	// decode active times of flash control signals;
	// simple and/or with flx_pipe pipe;

	wire flx_xle;				// ale/cle active decode;
	wire flx_xwe;				// we active decode;
	wire flx_xre;				// re active decode;

	assign flx_xle = |(flx_pipe & f_conf_ac);
	assign flx_xwe = |(flx_pipe & f_conf_we);
	assign flx_xre = |(flx_pipe & f_conf_re);

	assign f_cle = flx_cle & flx_xle;
	assign f_ale = flx_ale & flx_xle;
	assign f_we = flx_we & flx_xwe;
	assign f_re = flx_re & flx_xre;
	assign f_noe = flx_re & flx_busy;

	// device chip selects;
	// must be kept active for multi-cycle commands;
	// only one device can be active at a time;

	wire flx_ce;
	wire [1:0] flc_dev;

	assign flx_ce = sema;
	assign flc_dev = lba[27:26];

	assign f_ce[2] = flx_ce & (flc_dev == 2'd2);
	assign f_ce[1] = flx_ce & (flc_dev == 2'd1);
	assign f_ce[0] = flx_ce & (flc_dev == 2'd0);

endmodule