FDDRRSE.v
1.03 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
// $Header: /root/leakn64/depot/rf/hw/flif/xilinx/FDDRRSE.v,v 1.1 2003/08/20 23:46:46 berndt Exp $
/*
FUNCTION : Dual Data Rate MUX
*/
`timescale 100 ps / 10 ps
module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
parameter INIT = 1'h0;
output Q;
reg q_out;
input C0, C1, CE, D0, D1, R, S;
tri0 GSR = glbl.GSR;
buf B1 (Q, q_out);
always @(GSR)
if (GSR)
assign q_out = INIT;
else
deassign q_out;
always @(posedge C0)
if (R)
q_out <= 0;
else if (S)
q_out <= 1;
else if (CE)
q_out <= D0;
always @(posedge C1)
if (R)
q_out <= 0;
else if (S)
q_out <= 1;
else if (CE)
q_out <= D1;
specify
if (R)
(posedge C0 => (Q +: 1'b0)) = (1, 1);
if (!R && S)
(posedge C0 => (Q +: 1'b1)) = (1, 1);
if (!R && !S && CE)
(posedge C0 => (Q +: D0)) = (1, 1);
if (R)
(posedge C1 => (Q +: 1'b0)) = (1, 1);
if (!R && S)
(posedge C1 => (Q +: 1'b1)) = (1, 1);
if (!R && !S && CE)
(posedge C1 => (Q +: D1)) = (1, 1);
endspecify
endmodule